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Searched refs:VCC (Results 1 – 25 of 57) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIShrinkInstructions.cpp181 if (Use.isUse() && Use.getReg() == AMDGPU::VCC) { in copyFlagsToImplicitVCC()
440 MRI.setRegAllocationHint(MI.getOperand(0).getReg(), 0, AMDGPU::VCC); in runOnMachineFunction()
443 if (DstReg != AMDGPU::VCC) in runOnMachineFunction()
456 MRI.setRegAllocationHint(SReg, 0, AMDGPU::VCC); in runOnMachineFunction()
459 if (SReg != AMDGPU::VCC) in runOnMachineFunction()
472 if (SDst->getReg() != AMDGPU::VCC) { in runOnMachineFunction()
474 MRI.setRegAllocationHint(SDst->getReg(), 0, AMDGPU::VCC); in runOnMachineFunction()
480 if (Src2 && Src2->getReg() != AMDGPU::VCC) { in runOnMachineFunction()
482 MRI.setRegAllocationHint(Src2->getReg(), 0, AMDGPU::VCC); in runOnMachineFunction()
501 assert(MI.getOperand(0).getReg() == AMDGPU::VCC && in runOnMachineFunction()
DVOPCInstructions.td84 let Defs = [VCC];
173 let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
189 let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
561 let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
572 let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
DVOP2Instructions.td146 let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] in {
168 let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]) in {
264 // encoding normally allows them since the implicit VCC use means
267 // technically be possible to use VCC again as src0.
278 // implicit VCC use.
309 // implicit VCC use.
DSIRegisterInfo.td53 // VCC for 64-bit instructions
54 def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]>,
448 (add SGPR_64, VCC, FLAT_SCR, XNACK_MASK, TTMP_64, TBA, TMA)> {
DVOP3Instructions.td137 // only VOP instruction that implicitly reads VCC.
153 (i1 VCC)))];
308 let Uses = [VCC, EXEC] in {
327 } // End Uses = [VCC, EXEC]
DSOPInstructions.td619 // VCC = COPY SCC
620 // VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1
867 let Uses = [VCC] in {
876 } // End Uses = [VCC]
1033 // V_ADD_I32_e32/S_ADD_U32 produces carry in VCC/SCC. For the vector
DSIInsertSkips.cpp256 .addReg(AMDGPU::VCC, RegState::Define) in kill()
/external/llvm/lib/Target/AMDGPU/
DSIShrinkInstructions.cpp185 if (Use.getReg() == AMDGPU::VCC) { in copyFlagsToImplicitVCC()
338 MRI.setRegAllocationHint(MI.getOperand(0).getReg(), 0, AMDGPU::VCC); in runOnMachineFunction()
341 if (DstReg != AMDGPU::VCC) in runOnMachineFunction()
354 MRI.setRegAllocationHint(SReg, 0, AMDGPU::VCC); in runOnMachineFunction()
357 if (SReg != AMDGPU::VCC) in runOnMachineFunction()
374 assert(MI.getOperand(0).getReg() == AMDGPU::VCC && in runOnMachineFunction()
DSIInsertWaits.cpp552 } else if (!hasOutstandingLGKM() && I->modifiesRegister(AMDGPU::VCC, TRI)) { in runOnMachineFunction()
574 AMDGPU::VCC) in runOnMachineFunction()
575 .addReg(AMDGPU::VCC); in runOnMachineFunction()
DSIRegisterInfo.td26 // VCC for 64-bit instructions
27 def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]>,
279 (add SGPR_64, VCC, EXEC, FLAT_SCR, TTMP_64, TBA, TMA)> {
DSILowerControlFlow.cpp465 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), AMDGPU::VCC) in emitLoadM0FromVGPRLoop()
466 .addReg(AMDGPU::VCC); in emitLoadM0FromVGPRLoop()
480 .addReg(AMDGPU::VCC); in emitLoadM0FromVGPRLoop()
DSIInstrInfo.td642 int VCC = 0x6A;
1515 // encoding normally allows them since the implicit VCC use means
1518 // technically be possible to use VCC again as src0.
1526 // implicit VCC use.
1539 // implicit VCC use.
2022 // instead of an implicit VCC as in the VOP2b format.
2179 let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]) in {
2206 let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] in {
2289 let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
2304 let Defs = !if(DefExec, [VCC, EXEC], [VCC]);
[all …]
DAMDGPUISelDAGToDAG.cpp1351 SDValue VCC = CurDAG->getCopyToReg(N->getOperand(0), SL, AMDGPU::VCC, in SelectBRCOND() local
1357 VCC.getValue(0), // Chain in SelectBRCOND()
1358 VCC.getValue(1)); // Glue in SelectBRCOND()
/external/u-boot/drivers/power/
DKconfig85 save battery. On A31 devices dcdc1 is also used for VCC-IO. On A83T
86 dcdc1 is used for VCC-IO, nand, usb0, sd , etc. On A80 dcdc1 normally
120 On A10s boards with an axp152 dcdc3 is VCC-DRAM and should be 1.5V.
149 On A23 / A31 / A33 / A80 / A83T / R40 boards dcdc5 is VCC-DRAM and
162 On A23 / A33 boards aldo1 is used for VCC-IO and should be 3.0V.
194 On A23 / A31 / A33 / R40 boards aldo3 is VCC-PLL and AVCC and should
197 On A83T / H8 boards aldo3 is AVCC, VCC-PL, and VCC-LED, and should be
280 On A83T / H8 boards fldo1 is VCC-HSIC and should be 1.2V if HSIC is
290 On A83T / H8 boards fldo2 is VCC-CPUS and should be 0.9V.
/external/llvm/test/CodeGen/AMDGPU/
Dflat-scratch-reg.ll19 call void asm sideeffect "", "~{SGPR7},~{VCC}"()
37 call void asm sideeffect "", "~{SGPR7},~{VCC},~{FLAT_SCR}"()
/external/clang/test/CXX/concepts-ts/dcl.dcl/dcl.spec/dcl.spec.concept/
Dp2.cpp5 template<typename T> concept constexpr bool VCC = true; // expected-error {{variable concept cannot…
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/Disassembler/
DAMDGPUDisassembler.cpp278 insertNamedMCOperand(MI, createRegOperand(AMDGPU::VCC), in convertSDWAInst()
796 case 106: return createRegOperand(VCC); in decodeSpecialReg64()
869 return createRegOperand(AMDGPU::VCC); in decodeSDWAVopcDst()
/external/walt/hardware/kicad/
DWALTsm.net160 (pin (num 14) (name VCC) (type power_in))
161 (pin (num 15) (name VCC) (type power_in))
296 (pin (num 28) (name VCC) (type passive)))))
/external/u-boot/arch/arm/dts/
Ds5pc1xx-goni.dts103 regulator-name = "VCC+VCAM_2.8V";
Dsun8i-h3-bananapi-m2-plus.dts206 /* USB VBUS is on as long as VCC-IO is on */
Dat91-vinco.dts240 regulator-name = "VCC 3V3";
Dsun7i-a20-i12-tvbox.dts97 /* This controls VCC-PI, must be always on! */
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dframe-index-elimination.ll204 %vcc = call i64 asm sideeffect "; def $0", "={VCC}"()
208 call void asm sideeffect "; use $0", "{VCC}"(i64 %vcc)
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/MCTargetDesc/
DSIMCCodeEmitter.cpp369 if (Reg != AMDGPU::VCC) { in getSDWAVopcDstEncoding()
/external/llvm/lib/Target/AMDGPU/Disassembler/
DAMDGPUDisassembler.cpp420 case 106: return createRegOperand(VCC); in decodeSpecialReg64()

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