Searched refs:VR2 (Results 1 – 5 of 5) sorted by relevance
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonGenInsert.cpp | 201 bool operator() (unsigned VR1, unsigned VR2) const { in operator ()()
202 return operator[](VR1) < operator[](VR2); in operator ()()
277 bool operator() (unsigned VR1, unsigned VR2) const;
293 bool operator() (unsigned VR1, unsigned VR2) const;
303 bool RegisterCellLexCompare::operator() (unsigned VR1, unsigned VR2) const { in operator ()()
313 if (VR1 == VR2) in operator ()()
316 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1), &RC2 = CM.lookup(VR2); in operator ()()
327 return BitOrd.BaseOrd[VR1] < BitOrd.BaseOrd[VR2]; in operator ()()
331 bool RegisterCellBitCompareSel::operator() (unsigned VR1, unsigned VR2) const { in operator ()()
332 if (VR1 == VR2) in operator ()()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonGenInsert.cpp | 220 bool operator() (unsigned VR1, unsigned VR2) const { in operator ()()
221 return operator[](VR1) < operator[](VR2); in operator ()()
295 bool operator() (unsigned VR1, unsigned VR2) const;
313 bool operator() (unsigned VR1, unsigned VR2) const;
324 bool RegisterCellLexCompare::operator() (unsigned VR1, unsigned VR2) const { in operator ()()
334 if (VR1 == VR2) in operator ()()
337 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1), &RC2 = CM.lookup(VR2); in operator ()()
348 return BitOrd.BaseOrd[VR1] < BitOrd.BaseOrd[VR2]; in operator ()()
351 bool RegisterCellBitCompareSel::operator() (unsigned VR1, unsigned VR2) const { in operator ()()
352 if (VR1 == VR2) in operator ()()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 3045 unsigned VR2 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32() local
3046 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2) in emitBPOSGE32()
3058 .addReg(VR2) in emitBPOSGE32()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelLowering.cpp | 2954 unsigned VR2 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32() local
2955 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2) in emitBPOSGE32()
2967 .addReg(VR2) in emitBPOSGE32()
|
| /external/cldr/tools/java/org/unicode/cldr/util/data/external/ |
| D | 2013-1_UNLOCODE_CodeListPart1.csv | 43120 ,"FR","VR2","Vercheny","Vercheny","26","1----6--","RQ","0907",,"4443N 00515E",
|