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Searched refs:VReg1 (Results 1 – 3 of 3) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstructionSelector.cpp180 unsigned VReg1 = MIB->getOperand(1).getReg(); in selectMergeValues() local
181 (void)VReg1; in selectMergeValues()
182 assert(MRI.getType(VReg1).getSizeInBits() == 32 && in selectMergeValues()
183 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
211 unsigned VReg1 = MIB->getOperand(1).getReg(); in selectUnmergeValues() local
212 (void)VReg1; in selectUnmergeValues()
213 assert(MRI.getType(VReg1).getSizeInBits() == 32 && in selectUnmergeValues()
214 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
DARMISelLowering.cpp8478 unsigned VReg1 = MRI->createVirtualRegister(TRC); in EmitSjLjDispatchBlock() local
8479 BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), VReg1) in EmitSjLjDispatchBlock()
8483 unsigned VReg2 = VReg1; in EmitSjLjDispatchBlock()
8487 .addReg(VReg1) in EmitSjLjDispatchBlock()
8544 unsigned VReg1 = MRI->createVirtualRegister(TRC); in EmitSjLjDispatchBlock() local
8546 .addReg(VReg1, RegState::Define) in EmitSjLjDispatchBlock()
8551 .addReg(VReg1) in EmitSjLjDispatchBlock()
8616 unsigned VReg1 = MRI->createVirtualRegister(TRC); in EmitSjLjDispatchBlock() local
8617 BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1) in EmitSjLjDispatchBlock()
8621 unsigned VReg2 = VReg1; in EmitSjLjDispatchBlock()
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/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp7516 unsigned VReg1 = MRI->createVirtualRegister(TRC); in EmitSjLjDispatchBlock() local
7517 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::t2MOVi16), VReg1) in EmitSjLjDispatchBlock()
7520 unsigned VReg2 = VReg1; in EmitSjLjDispatchBlock()
7524 .addReg(VReg1) in EmitSjLjDispatchBlock()
7576 unsigned VReg1 = MRI->createVirtualRegister(TRC); in EmitSjLjDispatchBlock() local
7578 .addReg(VReg1, RegState::Define) in EmitSjLjDispatchBlock()
7582 .addReg(VReg1)); in EmitSjLjDispatchBlock()
7639 unsigned VReg1 = MRI->createVirtualRegister(TRC); in EmitSjLjDispatchBlock() local
7640 AddDefaultPred(BuildMI(DispatchBB, dl, TII->get(ARM::MOVi16), VReg1) in EmitSjLjDispatchBlock()
7643 unsigned VReg2 = VReg1; in EmitSjLjDispatchBlock()
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