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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCVInstrInfoA.td52 defm LR_W : LR_r_aq_rl<0b010, "lr.w">;
53 defm SC_W : AMO_rr_aq_rl<0b00011, 0b010, "sc.w">;
54 defm AMOSWAP_W : AMO_rr_aq_rl<0b00001, 0b010, "amoswap.w">;
55 defm AMOADD_W : AMO_rr_aq_rl<0b00000, 0b010, "amoadd.w">;
56 defm AMOXOR_W : AMO_rr_aq_rl<0b00100, 0b010, "amoxor.w">;
57 defm AMOAND_W : AMO_rr_aq_rl<0b01100, 0b010, "amoand.w">;
58 defm AMOOR_W : AMO_rr_aq_rl<0b01000, 0b010, "amoor.w">;
59 defm AMOMIN_W : AMO_rr_aq_rl<0b10000, 0b010, "amomin.w">;
60 defm AMOMAX_W : AMO_rr_aq_rl<0b10100, 0b010, "amomax.w">;
61 defm AMOMINU_W : AMO_rr_aq_rl<0b11000, 0b010, "amominu.w">;
[all …]
DRISCVInstrInfoF.td91 def FLW : RVInstI<0b010, OPC_LOAD_FP, (outs FPR32:$rd),
99 def FSW : RVInstS<0b010, OPC_STORE_FP, (outs),
128 def FSGNJX_S : FPALUS_rr<0b0010000, 0b010, "fsgnjx.s">;
146 def FEQ_S : FPCmpS_rr<0b010, "feq.s">;
DRISCVInstrInfoM.td22 def MULHSU : ALU_rr<0b0000001, 0b010, "mulhsu">;
DRISCVInstrInfo.td313 def LW : Load_ri<0b010, "lw">;
319 def SW : Store_rri<0b010, "sw">;
326 def SLTI : ALU_ri<0b010, "slti">;
339 def SLT : ALU_rr<0b0000000, 0b010, "slt">;
385 def CSRRS : CSR_ir<0b010, "csrrs">;
DRISCVInstrInfoD.td107 def FSGNJX_D : FPALUD_rr<0b0010001, 0b010, "fsgnjx.d">;
120 def FEQ_D : FPCmpD_rr<0b010, "feq.d">;
/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td41 def : AT<"S1E0R", 0b01, 0b000, 0b0111, 0b1000, 0b010>;
96 def : DC<"ISW", 0b01, 0b000, 0b0111, 0b0110, 0b010>;
98 def : DC<"CSW", 0b01, 0b000, 0b0111, 0b1010, 0b010>;
101 def : DC<"CISW", 0b01, 0b000, 0b0111, 0b1110, 0b010>;
239 def : TLBI<"ASIDE1IS", 0b01, 0b000, 0b1000, 0b0011, 0b010>;
255 def : TLBI<"ASIDE1", 0b01, 0b000, 0b1000, 0b0111, 0b010>;
329 def : ROSysReg<"ID_DFR0_EL1", 0b11, 0b000, 0b0000, 0b0001, 0b010>;
337 def : ROSysReg<"ID_ISAR2_EL1", 0b11, 0b000, 0b0000, 0b0010, 0b010>;
351 def : ROSysReg<"ID_AA64MMFR2_EL1", 0b11, 0b000, 0b0000, 0b0111, 0b010> {
356 def : ROSysReg<"MVFR2_EL1", 0b11, 0b000, 0b0000, 0b0011, 0b010>;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td41 def : AT<"S1E0R", 0b000, 0b0111, 0b1000, 0b010>;
98 def : DC<"ISW", 0b000, 0b0111, 0b0110, 0b010>;
100 def : DC<"CSW", 0b000, 0b0111, 0b1010, 0b010>;
103 def : DC<"CISW", 0b000, 0b0111, 0b1110, 0b010>;
344 def : TLBI<"ASIDE1IS", 0b000, 0b1000, 0b0011, 0b010>;
360 def : TLBI<"ASIDE1", 0b000, 0b1000, 0b0111, 0b010>;
374 def : TLBI<"ASIDE1OS", 0b000, 0b1000, 0b0001, 0b010>;
403 def : TLBI<"RIPAS2E1IS", 0b100, 0b1000, 0b0000, 0b010>;
405 def : TLBI<"RIPAS2E1", 0b100, 0b1000, 0b0100, 0b010>;
479 def : ROSysReg<"CCSIDR2_EL1", 0b11, 0b001, 0b0000, 0b0000, 0b010> {
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DAArch64SVEInstrInfo.td40 defm AND_ZPmZ : sve_int_bin_pred_log<0b010, "and">;
61 defm SMINV_VPZ : sve_int_reduce_1<0b010, "sminv">;
65 defm ANDV_VPZ : sve_int_reduce_2<0b010, "andv">;
78 defm SMULH_ZPmZ : sve_int_bin_pred_arit_2<0b010, "smulh">;
94 defm SXTH_ZPmZ : sve_int_un_pred_arit_0_w<0b010, "sxth">;
103 defm CNT_ZPmZ : sve_int_un_pred_arit_1< 0b010, "cnt">;
111 defm SMIN_ZPmZ : sve_int_bin_pred_arit_1<0b010, "smin">;
121 defm FMUL_ZPmI : sve_fp_2op_i_p_zds<0b010, "fmul", sve_fpimm_half_two>;
144 defm FMUL_ZZZ : sve_fp_3op_u_zd<0b010, "fmul">;
240 defm BRKAS_PPzP : sve_int_break_z<0b010, "brkas">;
[all …]
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.td193 def A2_addsat : T_ALU32_3op_sfx<"add", ":sat", 0b110, 0b010, 0, 1>;
880 def A2_vaddh : T_VectALU_64 < "vaddh", 0b000, 0b010, 0, 0, 0, 0>;
895 def A2_vavgub : T_VectALU_64 < "vavgub", 0b010, 0b000, 0, 0, 0, 0>;
896 def A2_vavgh : T_VectALU_64 < "vavgh", 0b010, 0b010, 0, 0, 0, 0>;
897 def A2_vavguh : T_VectALU_64 < "vavguh", 0b010, 0b101, 0, 0, 0, 0>;
903 def A2_vavgubr : T_VectALU_64 < "vavgub", 0b010, 0b001, 0, 1, 0, 0>;
904 def A2_vavghr : T_VectALU_64 < "vavgh", 0b010, 0b011, 0, 1, 0, 0>;
905 def A2_vavghcr : T_VectALU_64 < "vavgh", 0b010, 0b100, 0, 0, 1, 0>;
906 def A2_vavguhr : T_VectALU_64 < "vavguh", 0b010, 0b110, 0, 1, 0, 0>;
909 def A2_vavgwcr : T_VectALU_64 < "vavgw", 0b011, 0b010, 0, 0, 1, 0>;
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DHexagonInstrInfoVector.td75 def S2_asr_i_vw : vshift_v2i32<sra, "vasrw", 0b010, 0b000>;
76 def S2_lsr_i_vw : vshift_v2i32<srl, "vlsrw", 0b010, 0b001>;
77 def S2_asl_i_vw : vshift_v2i32<shl, "vaslw", 0b010, 0b010>;
81 def S2_asl_i_vh : vshift_v4i16<shl, "vaslh", 0b100, 0b010>;
DHexagonInstrInfoV5.td34 def M5_vmpybsu: T_XTYPE_mpy64 <"vmpybsu", 0b010, 0b001, 0, 0, 0>;
174 def F2_sfmpy : T_MInstFloat < "sfmpy", 0b010, 0b000>;
274 def F2_dfcmpge : T_fcmp64<"dfcmp.ge", setoge, 0b010>;
614 def F2_conv_d2sf : F2_RD_RSS_CONVERT <"convert_d2sf", 0b010,
620 def F2_conv_w2sf : F2_RD_RS_CONVERT <"convert_w2sf", 0b010, 0b000,
624 def F2_conv_ud2df : F2_RDD_RSS_CONVERT <"convert_ud2df", 0b010,
628 def F2_conv_w2df : F2_RDD_RS_CONVERT <"convert_w2df", 0b010,
DHexagonInstrInfoV4.td140 def A4_rcmpeq : T_ALU32_3op<"cmp.eq", 0b011, 0b010, 0, 1>;
187 def A4_cmpbgt : T_CMP_rrbh<"cmpb.gt", 0b010, 0>;
621 defm loadrh : ld_idxd_shl<"memh", "LDrih", IntRegs, 0b010>;
714 def S4_storerh_ap : T_ST_absset <"memh", "STrih", IntRegs, 0b010,
789 def S4_storerh_ur : T_StoreAbsReg <"memh", "STrih", IntRegs, 0b010,
1024 defm storerh: ST_Idxd_shl<"memh", "STrih", IntRegs, 0b010>,
1626 defm J4_cmpgtu : NVJrr_base<"cmp.gtu", "CMPGTU", 0b010, 0>, PredRel;
1686 defm J4_cmpgtui : NVJri_base<"cmp.gtu", "CMPGTU", 0b010>, PredRel;
1978 def S4_vxsubaddw : T_S3op_64 < "vxsubaddw", 0b01, 0b010, 0, 1>;
1983 def S4_vxsubaddhr : T_S3op_64 < "vxsubaddh", 0b11, 0b010, 0, 1, 1, 1>;
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DHexagonSystemInst.td74 "l2fetch($Rs, $Rt)", [], 0b011, 0b010, 0b0>;
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td407 class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>;
408 class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>;
409 class ADDS_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010000>;
410 class ADDS_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010000>;
569 class CLT_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001111>;
570 class CLT_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001111>;
571 class CLT_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001111>;
572 class CLT_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001111>;
579 class CLTI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000111>;
580 class CLTI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000111>;
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/external/mesa3d/src/intel/compiler/
Dbrw_reg_type.c100 GEN10_ALIGN1_3SRC_REG_TYPE_DF = 0b010,
106 GEN10_ALIGN1_3SRC_REG_TYPE_UW = 0b010,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td405 class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>;
406 class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>;
407 class ADDS_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010000>;
408 class ADDS_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010000>;
567 class CLT_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001111>;
568 class CLT_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001111>;
569 class CLT_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001111>;
570 class CLT_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001111>;
577 class CLTI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000111>;
578 class CLTI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000111>;
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/external/u-boot/doc/
DREADME.fsl-esdhc11 0b010 SD/MMC Legacy Card
/external/swiftshader/third_party/LLVM/test/TableGen/
Dif.td10 let n{8-6} = !if(x{2}, 0b010, 0b110);
/external/mesa3d/src/compiler/glsl/tests/
Darray_refcount_test.cpp671 operand b010 = deref_array( in TEST_F() local
685 deref_array(var_b, b010), in TEST_F()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonDepInstrInfo.td78 let Inst{7-5} = 0b010;
166 let Inst{7-5} = 0b010;
617 let Inst{7-5} = 0b010;
1089 let Inst{7-5} = 0b010;
1177 let Inst{7-5} = 0b010;
1671 let Inst{7-5} = 0b010;
1742 let Inst{7-5} = 0b010;
1833 let Inst{7-5} = 0b010;
1964 let Inst{7-5} = 0b010;
2024 let Inst{7-5} = 0b010;
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/external/llvm/test/TableGen/
Dif.td17 let n{8-6} = !if(x{2}, 0b010, 0b110);
/external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/
Dif.td17 let n{8-6} = !if(x{2}, 0b010, 0b110);
/external/llvm/lib/Target/Sparc/
DSparcInstr64Bit.td369 defm BPLEZ : BranchOnReg<0b010, "brlez">;
394 defm MOVRLEZ : MOVR<0b010, "movrlez">;
419 defm FMOVRLEZ : FMOVR<0b010, "lez">;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcInstr64Bit.td369 defm BPLEZ : BranchOnReg<0b010, "brlez">;
394 defm MOVRLEZ : MOVR<0b010, "movrlez">;
419 defm FMOVRLEZ : FMOVR<0b010, "lez">;
/external/llvm/lib/Target/Lanai/
DLanaiInstrInfo.td319 defm SUB_ : ALUarith<0b010, "sub", sub, i32lo16z, i32hi16>;
351 defm SUB_F_ : ALUarith<0b010, "sub.f", subc, i32lo16z, i32hi16>;
724 defm SFSUB_F : SF<0b010, "sub.f">;
824 def LEADZ: InstSpecial<0b010, (outs GPR:$Rd), (ins GPR:$Rs1),

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