Home
last modified time | relevance | path

Searched refs:brtarget (Results 1 – 25 of 73) sorted by relevance

123

/external/llvm/lib/Target/Sparc/
DSparcInstrAliases.td68 (BCOND brtarget:$imm, condVal)>;
72 (BCONDA brtarget:$imm, condVal)>;
76 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
80 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
84 (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
88 (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
92 (BPICCNT brtarget:$imm, condVal)>, Requires<[HasV9]>;
96 (BPICCANT brtarget:$imm, condVal)>, Requires<[HasV9]>;
100 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
104 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
[all …]
DSparcInstrInfo.td122 def brtarget : Operand<OtherVT> {
777 def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>;
827 def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
830 def BCONDA : BranchSPA<(ins brtarget:$imm22, CCOp:$cond),
867 def FBCOND : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
870 def FBCONDA : FPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
890 def CBCOND : CPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
893 def CBCONDA : CPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcInstrAliases.td68 (BCOND brtarget:$imm, condVal)>;
72 (BCONDA brtarget:$imm, condVal)>;
76 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
80 (BPICC brtarget:$imm, condVal)>, Requires<[HasV9]>;
84 (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
88 (BPICCA brtarget:$imm, condVal)>, Requires<[HasV9]>;
92 (BPICCNT brtarget:$imm, condVal)>, Requires<[HasV9]>;
96 (BPICCANT brtarget:$imm, condVal)>, Requires<[HasV9]>;
100 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
104 (BPXCC brtarget:$imm, condVal)>, Requires<[Is64Bit]>;
[all …]
DSparcInstrInfo.td125 def brtarget : Operand<OtherVT> {
781 def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>;
831 def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
834 def BCONDA : BranchSPA<(ins brtarget:$imm22, CCOp:$cond),
871 def FBCOND : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
874 def FBCONDA : FPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
894 def CBCOND : CPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
897 def CBCONDA : CPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
/external/capstone/arch/Sparc/
DSparcGenAsmWriter.inc1230 // (BCOND brtarget:$imm, 8)
1237 // (BCOND brtarget:$imm, 0)
1244 // (BCOND brtarget:$imm, 9)
1251 // (BCOND brtarget:$imm, 1)
1258 // (BCOND brtarget:$imm, 10)
1265 // (BCOND brtarget:$imm, 2)
1272 // (BCOND brtarget:$imm, 11)
1279 // (BCOND brtarget:$imm, 3)
1286 // (BCOND brtarget:$imm, 12)
1293 // (BCOND brtarget:$imm, 4)
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMips64r6InstrInfo.td81 class BGEC64_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR64Opnd>;
82 class BGEUC64_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR64Opnd>;
83 class BEQC64_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR64Opnd>;
84 class BNEC64_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR64Opnd>;
85 class BLTC64_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR64Opnd>;
86 class BLTUC64_DESC : CMP_BC_DESC_BASE<"bltuc", brtarget, GPR64Opnd>;
87 class BLTZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR64Opnd>;
88 class BGEZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR64Opnd>;
89 class BLEZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR64Opnd>;
90 class BGTZC64_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgtzc", brtarget, GPR64Opnd>;
DMips32r6InstrInfo.td419 class BAL_DESC : BC_DESC_BASE<"bal", brtarget> {
434 class BGEC_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR32Opnd>;
435 class BGEUC_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR32Opnd>;
436 class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
437 class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
439 class BLTC_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR32Opnd>;
440 class BLTUC_DESC : CMP_BC_DESC_BASE<"bltuc", brtarget, GPR32Opnd>;
442 class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd>;
443 class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd>;
445 class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>;
[all …]
DMipsInstrInfo.td824 def brtarget : Operand<OtherVT> {
1591 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], II_B>,
2007 (ins brtarget:$tgt, brtarget:$baltgt), []>;
2011 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
2216 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>,
2218 def BEQL : MMRel, CBranchLikely<"beql", brtarget, GPR32Opnd>,
2220 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>,
2222 def BNEL : MMRel, CBranchLikely<"bnel", brtarget, GPR32Opnd>,
2224 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
2226 def BGEZL : MMRel, CBranchZeroLikely<"bgezl", brtarget, GPR32Opnd>,
[all …]
DMips64InstrInfo.td257 def BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>,
259 def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>,
261 def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>,
263 def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>,
265 def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>,
267 def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>,
423 (ins GPR64Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>, GPR_64;
487 def BBIT0 : CBranchBitNum<"bbit0", brtarget, seteq, GPR64Opnd,
489 def BBIT032: CBranchBitNum<"bbit032", brtarget, seteq, GPR64Opnd, uimm5_64,
493 def BBIT1 : CBranchBitNum<"bbit1", brtarget, setne, GPR64Opnd,
[all …]
DMipsInstrFPU.td664 def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, II_BC1F, MIPS_BRANCH_F>,
666 def BC1FL : MMRel, BC1XL_FT<"bc1fl", brtarget, II_BC1FL>,
668 def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, II_BC1T, MIPS_BRANCH_T>,
670 def BC1TL : MMRel, BC1XL_FT<"bc1tl", brtarget, II_BC1TL>,
841 (BCTrue FCC0, brtarget:$offset), 1>;
844 (BCFalse FCC0, brtarget:$offset), 1>;
/external/llvm/lib/Target/Mips/
DMips32r6InstrInfo.td380 class BAL_DESC : BC_DESC_BASE<"bal", brtarget> {
395 class BGEC_DESC : CMP_BC_DESC_BASE<"bgec", brtarget, GPR32Opnd>;
396 class BGEUC_DESC : CMP_BC_DESC_BASE<"bgeuc", brtarget, GPR32Opnd>;
397 class BEQC_DESC : CMP_BC_DESC_BASE<"beqc", brtarget, GPR32Opnd>;
398 class BNEC_DESC : CMP_BC_DESC_BASE<"bnec", brtarget, GPR32Opnd>;
400 class BLTC_DESC : CMP_BC_DESC_BASE<"bltc", brtarget, GPR32Opnd>;
401 class BLTUC_DESC : CMP_BC_DESC_BASE<"bltuc", brtarget, GPR32Opnd>;
403 class BLTZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bltzc", brtarget, GPR32Opnd>;
404 class BGEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"bgezc", brtarget, GPR32Opnd>;
406 class BLEZC_DESC : CMP_CBR_RT_Z_DESC_BASE<"blezc", brtarget, GPR32Opnd>;
[all …]
DMips64InstrInfo.td236 def BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>;
237 def BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>;
238 def BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>;
239 def BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>;
240 def BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>;
241 def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>;
347 (ins GPR64Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
410 def BBIT0 : CBranchBitNum<"bbit0", brtarget, seteq, GPR64Opnd,
412 def BBIT032: CBranchBitNum<"bbit032", brtarget, seteq, GPR64Opnd, uimm5_64,
416 def BBIT1 : CBranchBitNum<"bbit1", brtarget, setne, GPR64Opnd,
[all …]
DMipsInstrInfo.td626 def brtarget : Operand<OtherVT> {
1303 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], II_B>,
1304 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
1366 PseudoSE<(outs), (ins brtarget:$offset), [], II_BCCZAL>,
1367 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
1658 (ins brtarget:$tgt, brtarget:$baltgt), []>;
1662 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
1860 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1861 def BEQL : MMRel, CBranch<"beql", brtarget, seteq, GPR32Opnd, 0>,
1863 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
[all …]
DMipsInstrFPU.td528 def BC1F : MMRel, BC1F_FT<"bc1f", brtarget, II_BC1F, MIPS_BRANCH_F>,
530 def BC1FL : MMRel, BC1F_FT<"bc1fl", brtarget, II_BC1FL, MIPS_BRANCH_F, 0>,
532 def BC1T : MMRel, BC1F_FT<"bc1t", brtarget, II_BC1T, MIPS_BRANCH_T>,
534 def BC1TL : MMRel, BC1F_FT<"bc1tl", brtarget, II_BC1TL, MIPS_BRANCH_T, 0>,
593 def : MipsInstAlias<"bc1t $offset", (BC1T FCC0, brtarget:$offset)>,
595 def : MipsInstAlias<"bc1tl $offset", (BC1TL FCC0, brtarget:$offset)>,
597 def : MipsInstAlias<"bc1f $offset", (BC1F FCC0, brtarget:$offset)>,
599 def : MipsInstAlias<"bc1fl $offset", (BC1FL FCC0, brtarget:$offset)>,
/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/
DSystemZInstrInfo.td101 def JMP : Pseudo<(outs), (ins brtarget:$dst), "j\t{$dst}", [(br bb:$dst)]>;
108 def JO : Pseudo<(outs), (ins brtarget:$dst),
111 def JH : Pseudo<(outs), (ins brtarget:$dst),
114 def JNLE: Pseudo<(outs), (ins brtarget:$dst),
117 def JL : Pseudo<(outs), (ins brtarget:$dst),
120 def JNHE: Pseudo<(outs), (ins brtarget:$dst),
123 def JLH : Pseudo<(outs), (ins brtarget:$dst),
126 def JNE : Pseudo<(outs), (ins brtarget:$dst),
129 def JE : Pseudo<(outs), (ins brtarget:$dst),
132 def JNLH: Pseudo<(outs), (ins brtarget:$dst),
[all …]
/external/llvm/lib/Target/BPF/
DBPFInstrInfo.td46 def brtarget : Operand<OtherVT>;
83 : InstBPF<(outs), (ins GPR:$dst, GPR:$src, brtarget:$BrDst),
104 : InstBPF<(outs), (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst),
353 : InstBPF<(outs), (ins brtarget:$BrDst),
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrControl.td42 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
46 def JMP64pcrel32 : I<0xE9, RawFrm, (outs), (ins brtarget:$dst),
54 def _4 : Ii32PCRel<opc4, RawFrm, (outs), (ins brtarget:$dst), asm,
/external/swiftshader/third_party/LLVM/lib/Target/XCore/
DXCoreInstrInfo.td172 def brtarget : Operand<OtherVT>;
280 (outs), (ins GRRegs:$cond, brtarget:$dest),
284 (outs), (ins GRRegs:$cond, brtarget:$dest),
671 (ins brtarget:$target),
677 (ins brtarget:$target),
683 (ins brtarget:$target),
689 (ins brtarget:$target),
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/
DBPFInstrInfo.td58 def brtarget : Operand<OtherVT> {
141 (ins GPR:$dst, GPR:$src, brtarget:$BrDst),
157 (ins GPR:$dst, i64imm:$imm, brtarget:$BrDst),
399 (ins brtarget:$BrDst),
/external/llvm/lib/Target/Hexagon/
DHexagonInstrAlias.td475 (J2_jumpf PredRegs:$Pu, brtarget:$r15_2)>,
480 (J2_jumpt PredRegs:$Pu, brtarget:$r15_2)>,
484 (J2_jumpt PredRegs:$src, brtarget:$r15_2), 0>;
487 (J2_jumpf PredRegs:$src, brtarget:$r15_2), 0>;
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsInstrInfo.td141 def brtarget : Operand<OtherVT>;
402 CBranchBase<op, (outs), (ins RC:$rs, RC:$rt, brtarget:$imm16),
412 CBranchBase<op, (outs), (ins RC:$rs, brtarget:$imm16),
441 FJ<op, (outs), (ins brtarget:$target),
472 FI<0x1, (outs), (ins CPURegs:$rs, brtarget:$imm16, variable_ops),
/external/capstone/arch/Mips/
DMipsGenAsmWriter.inc5083 // (BC0F CC0, brtarget:$offset)
5091 // (BC0FL CC0, brtarget:$offset)
5099 // (BC0T CC0, brtarget:$offset)
5107 // (BC0TL CC0, brtarget:$offset)
5115 // (BC1F FCC0, brtarget:$offset)
5123 // (BC1FL FCC0, brtarget:$offset)
5131 // (BC1T FCC0, brtarget:$offset)
5139 // (BC1TL FCC0, brtarget:$offset)
5147 // (BC2F CC0, brtarget:$offset)
5155 // (BC2FL CC0, brtarget:$offset)
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/Sparc/
DSparcInstrInfo.td80 def brtarget : Operand<OtherVT>;
514 def BA : BranchSP<0b1000, (ins brtarget:$dst),
520 def BCOND : BranchSP<0, (ins brtarget:$dst, CCOp:$cc),
537 def FBCOND : FPBranchSP<0, (ins brtarget:$dst, CCOp:$cc),
/external/llvm/lib/Target/AMDGPU/
DR600Instructions.td1299 (ins brtarget:$target, R600_Predicate_Bit:$p),
1306 (ins brtarget:$target),
1499 (ins brtarget:$target, rci:$src0),
1503 (ins brtarget:$target, rcf:$src0),
1528 def BRANCH : ILFormat<(outs), (ins brtarget:$target),
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIInstructions.td213 (outs), (ins brtarget:$target)> {
228 (ins SReg_64:$vcc, brtarget:$target),
235 (outs SReg_64:$dst), (ins SReg_64:$vcc, brtarget:$target),
244 (ins SReg_64:$src, brtarget:$target, i1imm:$execfix), [], 1, 1> {
250 (outs), (ins SReg_64:$saved, brtarget:$target),

123