Searched refs:clk_ctrl (Results 1 – 5 of 5) sorted by relevance
101 static enum zynq_clk zynq_clk_get_cpu_pll(u32 clk_ctrl) in zynq_clk_get_cpu_pll() argument103 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT; in zynq_clk_get_cpu_pll()116 static enum zynq_clk zynq_clk_get_peripheral_pll(u32 clk_ctrl) in zynq_clk_get_peripheral_pll() argument118 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> CLK_CTRL_SRCSEL_SHIFT; in zynq_clk_get_peripheral_pll()133 u32 clk_ctrl, reset, pwrdwn, mul, bypass; in zynq_clk_get_pll_rate() local135 clk_ctrl = readl(zynq_clk_get_register(id)); in zynq_clk_get_pll_rate()137 reset = (clk_ctrl & PLLCTRL_RESET_MASK) >> PLLCTRL_RESET_SHIFT; in zynq_clk_get_pll_rate()138 pwrdwn = (clk_ctrl & PLLCTRL_PWRDWN_MASK) >> PLLCTRL_PWRDWN_SHIFT; in zynq_clk_get_pll_rate()142 bypass = clk_ctrl & PLLCTRL_BPFORCE_MASK; in zynq_clk_get_pll_rate()146 mul = (clk_ctrl & PLLCTRL_FBDIV_MASK) >> PLLCTRL_FBDIV_SHIFT; in zynq_clk_get_pll_rate()[all …]
244 static enum zynqmp_clk zynqmp_clk_get_cpu_pll(u32 clk_ctrl) in zynqmp_clk_get_cpu_pll() argument246 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> in zynqmp_clk_get_cpu_pll()260 static enum zynqmp_clk zynqmp_clk_get_ddr_pll(u32 clk_ctrl) in zynqmp_clk_get_ddr_pll() argument262 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> in zynqmp_clk_get_ddr_pll()274 static enum zynqmp_clk zynqmp_clk_get_peripheral_pll(u32 clk_ctrl) in zynqmp_clk_get_peripheral_pll() argument276 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> in zynqmp_clk_get_peripheral_pll()290 static enum zynqmp_clk zynqmp_clk_get_wdt_pll(u32 clk_ctrl) in zynqmp_clk_get_wdt_pll() argument292 u32 srcsel = (clk_ctrl & CLK_CTRL_SRCSEL_MASK) >> in zynqmp_clk_get_wdt_pll()306 static ulong zynqmp_clk_get_pll_src(ulong clk_ctrl, in zynqmp_clk_get_pll_src() argument313 src_sel = (clk_ctrl & PLLCTRL_POST_SRC_MASK) >> in zynqmp_clk_get_pll_src()[all …]
32 struct ccsr_clk_ctrl __iomem *clk_ctrl = in get_sys_info() local117 c_pll_sel = (in_le32(&clk_ctrl->clkcncsr[cluster].csr) >> 27) in get_sys_info()
18 u32 clk_ctrl; /* Timer clk control reg */ member111 writel(0x0, &armd1timers->clk_ctrl); in timer_init()
84 u32 clk_ctrl; member132 writel(readl(&priv->base->clk_ctrl) & ~QSPI_CLK_EN, in ti_spi_set_speed()133 &priv->base->clk_ctrl); in ti_spi_set_speed()135 writel(QSPI_CLK_EN | clk_div, &priv->base->clk_ctrl); in ti_spi_set_speed()