Searched refs:conv8 (Results 1 – 25 of 80) sorted by relevance
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| /external/swiftshader/third_party/LLVM/test/CodeGen/X86/ |
| D | 2009-11-18-TwoAddrKill.ll | 12 %conv8 = trunc i16 %tmp17 to i8 ; <i8> [#uses=3]
20 %tmp = sub i8 0, %conv8 ; <i8> [#uses=1]
21 %mul.i = and i8 %conv8, %tmp ; <i8> [#uses=1]
25 %call1231 = phi i8 [ %mul.i, %cond.false.i29 ], [ %conv8, %land.lhs.true.i ] ; <i8> [#uses=0]
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| /external/llvm/test/CodeGen/X86/ |
| D | 2009-11-18-TwoAddrKill.ll | 12 %conv8 = trunc i16 %tmp17 to i8 ; <i8> [#uses=3]
20 %tmp = sub i8 0, %conv8 ; <i8> [#uses=1]
21 %mul.i = and i8 %conv8, %tmp ; <i8> [#uses=1]
25 %call1231 = phi i8 [ %mul.i, %cond.false.i29 ], [ %conv8, %land.lhs.true.i ] ; <i8> [#uses=0]
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/ |
| D | 2009-11-18-TwoAddrKill.ll | 12 %conv8 = trunc i16 %tmp17 to i8 ; <i8> [#uses=3]
20 %tmp = sub i8 0, %conv8 ; <i8> [#uses=1]
21 %mul.i = and i8 %conv8, %tmp ; <i8> [#uses=1]
25 %call1231 = phi i8 [ %mul.i, %cond.false.i29 ], [ %conv8, %land.lhs.true.i ] ; <i8> [#uses=0]
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| D | pr32420.ll | 30 %conv8 = or i16 %t2, %ashr4
34 %and = and i16 %conv8, %ashr11
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| D | pr33828.ll | 33 %conv8 = zext i16 %phitmp to i32
34 %mul = shl nuw nsw i32 %conv8, 1
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/ |
| D | vec_int_ext.ll | 27 %conv8 = sext i8 %vecext7 to i32
28 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
75 %conv8 = sext i16 %vecext7 to i32
76 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
143 %conv8 = sext i8 %vecext7 to i32
144 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
189 %conv8 = sext i16 %vecext7 to i32
190 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
272 %conv8 = sext i8 %vecext7 to i16
273 %vecinit9 = insertelement <8 x i16> %vecinit6, i16 %conv8, i32 3
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SLPVectorizer/X86/ |
| D | sign-extend.ll | 29 %conv8 = sext i16 %vecext7 to i32
30 %vecinit9 = insertelement <4 x i32> %vecinit6, i32 %conv8, i32 3
59 %conv8 = trunc i32 %vecext7 to i16
60 %vecinit9 = insertelement <4 x i16> %vecinit6, i16 %conv8, i32 3
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | smlad1.ll | 41 %conv8 = sext i16 %1 to i32
42 %mul9 = mul nsw i32 %conv7, %conv8
87 %conv8 = sext i8 %1 to i32
88 %mul9 = mul nsw i32 %conv7, %conv8
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| D | smlad5.ll | 37 %conv8 = sext i16 %1 to i32
38 %mul9 = mul nsw i32 %conv7, %conv8
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| D | smlad10.ll | 38 %conv8 = sext i16 %1 to i64
39 %mul9 = mul nsw i64 %conv7, %conv8
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| D | smlad12.ll | 38 %conv8 = sext i16 %1 to i32
39 %mul9 = mul nsw i32 %conv7, %conv8
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| D | smlad3.ll | 43 %conv8 = sext i16 %1 to i32
44 %mul9 = mul nsw i32 %conv7, %conv8
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| D | smlad2.ll | 44 %conv8 = sext i16 %1 to i32
46 %mul9 = mul nsw i32 %conv7, %conv8
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| D | smlad6.ll | 43 %conv8 = sext i16 %1 to i32
44 %mul9 = mul nsw i32 %conv7, %conv8
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| D | smlad7.ll | 43 %conv8 = sext i16 %1 to i32
44 %mul9 = mul nsw i32 %conv7, %conv8
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| D | smlad8.ll | 49 %conv8 = sext i16 %1 to i32
53 %mul9 = mul nsw i32 %add2, %conv8
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| /external/llvm/test/CodeGen/NVPTX/ |
| D | addrspacecast.ll | 89 define i32 @conv8(i32* %ptr) {
90 ; PTX32: conv8
93 ; PTX64: conv8
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| /external/llvm/test/Transforms/LoopVectorize/ |
| D | i8-induction.ll | 17 %c.015 = phi i8 [ undef, %scalar.ph ], [ %conv8, %for.body ]
23 %conv8 = trunc i32 %add to i8
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| /external/swiftshader/third_party/LLVM/test/CodeGen/Thumb/ |
| D | rev.ll | 54 %conv8 = ashr exact i32 %sext, 16
55 ret i32 %conv8
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopVectorize/ |
| D | i8-induction.ll | 23 %c.015 = phi i8 [ undef, %scalar.ph ], [ %conv8, %for.body ]
29 %conv8 = trunc i32 %add to i8
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| /external/llvm/test/CodeGen/Thumb/ |
| D | rev.ll | 54 %conv8 = ashr exact i32 %sext, 16
55 ret i32 %conv8
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Thumb/ |
| D | rev.ll | 54 %conv8 = ashr exact i32 %sext, 16
55 ret i32 %conv8
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| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-addr-mode-folding.ll | 25 %conv8 = zext i1 %cmp7 to i32
63 …%retval.0 = phi i32 [ %conv8, %if.then ], [ %conv22, %if.then18 ], [ %conv38, %if.then34 ], [ 1, %…
85 %conv8 = zext i1 %cmp7 to i32
123 …%retval.0 = phi i32 [ %conv8, %if.then ], [ %conv22, %if.then18 ], [ %conv38, %if.then34 ], [ 1, %…
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | arm64-addr-mode-folding.ll | 25 %conv8 = zext i1 %cmp7 to i32
63 …%retval.0 = phi i32 [ %conv8, %if.then ], [ %conv22, %if.then18 ], [ %conv38, %if.then34 ], [ 1, %…
85 %conv8 = zext i1 %cmp7 to i32
123 …%retval.0 = phi i32 [ %conv8, %if.then ], [ %conv22, %if.then18 ], [ %conv38, %if.then34 ], [ 1, %…
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopDeletion/ |
| D | update-scev.ll | 41 %conv8 = ashr exact i32 %sext, 24
42 %cmp9 = icmp eq i32 %conv8, %f.0
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