Searched refs:fp5 (Results 1 – 14 of 14) sorted by relevance
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/ |
| D | 2010-05-12-FastAllocKills.ll | 12 …%fp1, implicit-def %fp2, implicit-def %fp3, implicit-def %fp4, implicit-def %fp5, implicit-def %fp6
26 …%fp1, implicit-def %fp2, implicit-def %fp3, implicit-def %fp4, implicit-def %fp5, implicit-def %fp6
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| D | ipra-reg-usage.ll | 6 …r7 $dr8 $dr9 $dr10 $dr11 $dr12 $dr13 $dr14 $dr15 $fp0 $fp1 $fp2 $fp3 $fp4 $fp5 $fp6 $fp7 $k0 $k1 $…
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| /external/clang/test/SemaTemplate/ |
| D | member-template-access-expr.cpp | 73 float* (*fp5)(float) = &X1::f2<float>; in test_X1() local
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| /external/clang/test/SemaCXX/ |
| D | cxx1y-generic-lambdas.cpp | 185 char (*fp5)(char) = [](auto e) -> int { return e; }; //expected-error{{no viable conversion}}\ in test() local
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| /external/elfutils/tests/ |
| D | run-readelf-mixed-corenote.sh | 645 fp4: 0x7fff0000ffffffffffffffff fp5: 0x7fff0000ffffffffffffffff
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| D | run-allregs.sh | 2901 21: %fp5 (fp5), float 96 bits
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| /external/swiftshader/third_party/LLVM/lib/Target/X86/ |
| D | X86RegisterInfo.td | 162 def FP5 : Register<"fp5">;
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| D | X86GenAsmWriter.inc | 5435 "\000esp\000fp0\000fp1\000fp2\000fp3\000fp4\000fp5\000fp6\000fs\000gs\000"
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| D | X86GenAsmWriter1.inc | 6178 "\000esp\000fp0\000fp1\000fp2\000fp3\000fp4\000fp5\000fp6\000fs\000gs\000"
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| D | X86GenAsmMatcher.inc | 263 return 60; // "fp5"
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| /external/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.td | 167 def FP5 : X86Reg<"fp5", 0>;
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.td | 206 def FP5 : X86Reg<"fp5", 0>;
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| /external/honggfuzz/examples/apache-httpd/corpus_http1/ |
| D | d697e5ee9dbfb4c9dbc3fea2b0efed48.0000f4ac.honggfuzz.cov | 339 …6x�C��e��� ��C4���~�4��N%��:Һ�[⋀��7N�xJ�9�z��,��z�[x��uB?Vńno��#����;fp5ǯ��&�k�/�2�/���:J:��…
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/ |
| D | X86GenAsmMatcher.inc | 296 return 106; // "fp5"
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