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Searched refs:fpround (Results 1 – 25 of 33) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DVOP3PInstructions.td76 (f16 (fpround (fma_like (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_modifiers)),
90 …(build_vector f16:$elt0, (fpround (fma_like (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_modifiers)),
103 (AMDGPUclamp (fpround (fma_like (f32 (VOP3PMadMixMods f16:$src0, i32:$src0_modifiers)),
115 (fpround (fma_like (f32 (VOP3PMadMixMods f16:$lo_src0, i32:$lo_src0_modifiers)),
118 (fpround (fma_like (f32 (VOP3PMadMixMods f16:$hi_src0, i32:$hi_src0_modifiers)),
DVOP1Instructions.td176 defm V_CVT_F16_F32 : VOP1Inst <"v_cvt_f16_f32", VOP_F16_F32, fpround>;
181 defm V_CVT_F32_F64 : VOP1Inst <"v_cvt_f32_f64", VOP_F32_F64, fpround>;
/external/libpng/contrib/libtests/
Dtarith.c640 long long int fp, fpround; in validation_muldiv() local
680 fpround = fp; in validation_muldiv()
682 ok = fpround <= PNG_UINT_31_MAX && in validation_muldiv()
683 fpround >= -1-(long long int)PNG_UINT_31_MAX; in validation_muldiv()
687 ok = 0, ++overflow, fpround = fp/*misleading*/; in validation_muldiv()
704 else if (ok && result != fpround) in validation_muldiv()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZInstrFP.td96 def : Pat<(fcopysign FP32:$src1, (f32 (fpround (f128 FP128:$src2)))),
99 def : Pat<(fcopysign FP32:$src1, (f32 (fpround (f128 VR128:$src2)))),
109 def : Pat<(fcopysign FP64:$src1, (f64 (fpround (f128 FP128:$src2)))),
112 def : Pat<(fcopysign FP64:$src1, (f64 (fpround (f128 VR128:$src2)))),
177 def LEDBR : UnaryRRE<"ledbr", 0xB344, fpround, FP32, FP64>;
189 def : Pat<(f32 (fpround FP128:$src)),
191 def : Pat<(f64 (fpround FP128:$src)),
DSystemZInstrVector.td1018 def : FPConversion<WLEDB, fpround, v32sb, v64db, 0, 0>;
1026 def : FPConversion<WFLRX, fpround, v64db, v128xb, 0, 0>;
1027 def : Pat<(f32 (fpround (f128 VR128:$src))),
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dfneg-combines.ll1171 %fpround = fptrunc double %a to float
1172 %fneg = fsub float -0.000000e+00, %fpround
1188 %fpround = fptrunc double %fneg.a to float
1189 %fneg = fsub float -0.000000e+00, %fpround
1207 %fpround = fptrunc double %fneg.a to float
1208 %fneg = fsub float -0.000000e+00, %fpround
1227 %fpround = fptrunc double %fneg.a to float
1228 %fneg = fsub float -0.000000e+00, %fpround
1245 %fpround = fptrunc float %a to half
1246 %fneg = fsub half -0.000000e+00, %fpround
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/GlobalISel/
DSelectionDAGCompat.td66 def : GINodeEquiv<G_FPTRUNC, fpround>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMicroMipsInstrFPU.td412 def : MipsPat<(f32 (fpround FGR64Opnd:$src)),
416 def : MipsPat<(f32 (fpround AFGR64Opnd:$src)),
DMipsInstrFPU.td879 def : MipsPat<(f32 (fpround AFGR64Opnd:$src)),
904 def : MipsPat<(f32 (fpround FGR64Opnd:$src)),
DMipsMSAInstrInfo.td3776 (f16 (fpround FGR32Opnd:$fs)))]> {
3790 (f16 (fpround FGR64Opnd:$fs)))]> {
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCVInstrInfoD.td212 def : Pat<(fpround FPR64:$rs1), (FCVT_S_D FPR64:$rs1, 0b111)>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrConv.td201 [(set F32:$dst, (fpround F64:$src))],
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrFPStack.td734 def : Pat<(f32 (fpround RFP64:$src)), (COPY_TO_REGCLASS RFP64:$src, RFP32)>,
736 def : Pat<(f32 (fpround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP32)>,
738 def : Pat<(f64 (fpround RFP80:$src)), (COPY_TO_REGCLASS RFP80:$src, RFP64)>,
DX86InstrSSE.td1192 def : Pat<(f32 (fpround FR64:$src)),
1198 [(set FR32:$dst, (fpround FR64:$src))]>,
1202 [(set FR32:$dst, (fpround (loadf64 addr:$src)))]>,
1321 (f32 (fpround (f64 (extractelt VR128:$src, (iPTR 0))))))))),
1375 (f32 (fpround (f64 (extractelt VR128:$src, (iPTR 0))))))))),
1766 [(set VR128:$dst, (fpround VR256:$src))]>,
1770 [(set VR128:$dst, (fpround (loadv4f64 addr:$src)))]>,
1792 // Match fpround and fpextend for 128/256-bit conversions
1802 // Match fpround and fpextend for 128 conversions
DX86InstrAVX512.td7624 def : Pat<(f32 (fpround FR64X:$src)),
7631 (f32 (fpround (f64 (extractelt VR128X:$src, (iPTR 0))))))))),
7715 defm Z : avx512_vcvt_fp<opc, OpcodeStr, v8f32x_info, v8f64_info, fpround, sched.ZMM>,
7722 defm Z256 : avx512_vcvt_fp<opc, OpcodeStr, v4f32x_info, v4f64x_info, fpround,
8277 def : Pat<(v8f32 (fpround (loadv8f64 addr:$src))),
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.td2949 // fpround f32 -> f16
2950 def : Pat<(f16 (fpround Float32Regs:$a)),
2952 def : Pat<(f16 (fpround Float32Regs:$a)),
2955 // fpround f64 -> f16
2956 def : Pat<(f16 (fpround Float64Regs:$a)),
2958 def : Pat<(f16 (fpround Float64Regs:$a)),
2961 // fpround f64 -> f32
2962 def : Pat<(f32 (fpround Float64Regs:$a)),
2964 def : Pat<(f32 (fpround Float64Regs:$a)),
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCInstrVSX.td1289 def : Pat<(f32 (fpround (f64 (extloadf32 xoaddr:$src)))),
3257 def : Pat<(f32 (fpround (f64 (extloadf32 ixaddr:$src)))),
3515 def : Pat<(f64 (fpround f128:$src)), (f64 (XSCVQPDP $src))>;
3516 def : Pat<(f32 (fpround f128:$src)), (f32 (XSRSP (XSCVQPDPO $src)))>;
3563 dag A0 = (f32 (fpround (f64 (extractelt v2f64:$A, 0))));
3564 dag A1 = (f32 (fpround (f64 (extractelt v2f64:$A, 1))));
3565 dag B0 = (f32 (fpround (f64 (extractelt v2f64:$B, 0))));
3566 dag B1 = (f32 (fpround (f64 (extractelt v2f64:$B, 1))));
DPPCInstrQPX.td91 def fround_inexact : PatFrag<(ops node:$val), (fpround node:$val), [{
95 def fround_exact : PatFrag<(ops node:$val), (fpround node:$val), [{
DPPCInstrSPE.td258 [(set f32:$RT, (fpround f64:$RB))]>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcInstrInfo.td1151 [(set f32:$rd, (fpround f64:$rs2))],
1161 [(set f32:$rd, (fpround f128:$rs2))]>,
1166 [(set f64:$rd, (fpround f128:$rs2))]>,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrVFP.td657 [(set SPR:$Sd, (fpround DPR:$Dm))]>,
696 def : FullFP16Pat<(f16 (fpround SPR:$Sm)),
748 def : FullFP16Pat<(f16 (fpround DPR:$Dm)),
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/
DTargetSelectionDAG.td437 def fpround : SDNode<"ISD::FP_ROUND" , SDTFPRoundOp>;
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenGlobalISel.inc13810 … // (fpround:{ *:[f32] } FR64:{ *:[f64] }:$src) => (CVTSD2SSrr:{ *:[f32] } FR64:{ *:[f64] }:$src)
13821 …// (fpround:{ *:[f32] } RFP64:{ *:[f64] }:$src) => (COPY_TO_REGCLASS:{ *:[f32] } RFP64:{ *:[f64]…
13832 …// (fpround:{ *:[f32] } RFP80:{ *:[f80] }:$src) => (COPY_TO_REGCLASS:{ *:[f32] } RFP80:{ *:[f80]…
13843 …// (fpround:{ *:[f32] } FR64:{ *:[f64] }:$src) => (VCVTSD2SSrr:{ *:[f32] } (IMPLICIT_DEF:{ *:[f3…
13862 …// (fpround:{ *:[f32] } FR64X:{ *:[f64] }:$src) => (VCVTSD2SSZrr:{ *:[f32] } (IMPLICIT_DEF:{ *:[…
13883 …// (fpround:{ *:[f64] } RFP80:{ *:[f80] }:$src) => (COPY_TO_REGCLASS:{ *:[f64] } RFP80:{ *:[f80]…
13897 …// (fpround:{ *:[v4f32] } VR256:{ *:[v4f64] }:$src) => (VCVTPD2PSYrr:{ *:[v4f32] } VR256:{ *:[v4…
13907 …// (fpround:{ *:[v4f32] } VR256X:{ *:[v4f64] }:$src) => (VCVTPD2PSZ256rr:{ *:[v4f32] } VR256X:{ …
13922 …// (fpround:{ *:[v8f32] } VR512:{ *:[v8f64] }:$src) => (VCVTPD2PSZrr:{ *:[v8f32] } VR512:{ *:[v8…
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenGlobalISel.inc15220 …// (fpround:{ *:[f16] } FGR32Opnd:{ *:[f32] }:$fs) => (MSA_FP_ROUND_W_PSEUDO:{ *:[f16] } FGR32Op…
15231 …// (fpround:{ *:[f16] } FGR64Opnd:{ *:[f64] }:$fs) => (MSA_FP_ROUND_D_PSEUDO:{ *:[f16] } FGR64Op…
15245 …// (fpround:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D32:{ *:[f32] } AFGR64Opnd:{ *:[f…
15254 …// (fpround:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D64:{ *:[f32] } FGR64Opnd:{ *:[f64…
15263 …// (fpround:{ *:[f32] } FGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D64_MM:{ *:[f32] } FGR64Opnd:{ *:[…
15272 …// (fpround:{ *:[f32] } AFGR64Opnd:{ *:[f64] }:$src) => (CVT_S_D32_MM:{ *:[f32] } AFGR64Opnd:{ *…
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td3075 def : Pat<(v2f32 (fpround (v2f64 V128:$Rn))), (FCVTNv2i32 V128:$Rn)>;
3076 def : Pat<(v4f16 (fpround (v4f32 V128:$Rn))), (FCVTNv4i16 V128:$Rn)>;
3077 def : Pat<(concat_vectors V64:$Rd, (v2f32 (fpround (v2f64 V128:$Rn)))),

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