| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64StorePairSuppress.cpp | 153 if (TII->getMemOpBaseRegImmOfs(MI, BaseReg, Offset, TRI)) { in runOnMachineFunction()
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| D | AArch64InstrInfo.h | 113 bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64StorePairSuppress.cpp | 148 if (TII->getMemOpBaseRegImmOfs(MI, BaseReg, Offset, TRI)) { in runOnMachineFunction()
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| D | AArch64InstrInfo.h | 96 bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
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| /external/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.h | 70 bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
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| D | LanaiInstrInfo.cpp | 787 bool LanaiInstrInfo::getMemOpBaseRegImmOfs( in getMemOpBaseRegImmOfs() function in LanaiInstrInfo
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/ |
| D | LanaiInstrInfo.h | 71 bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
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| D | LanaiInstrInfo.cpp | 790 bool LanaiInstrInfo::getMemOpBaseRegImmOfs( in getMemOpBaseRegImmOfs() function in LanaiInstrInfo
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.h | 192 bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
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| /external/llvm/lib/CodeGen/ |
| D | ImplicitNullChecks.cpp | 428 if (TII->getMemOpBaseRegImmOfs(MI, BaseReg, Offset, TRI)) in analyzeBlockForNullChecks()
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| D | MachineSink.cpp | 700 if (!TII->getMemOpBaseRegImmOfs(MI, BaseReg, Offset, TRI)) in SinkingPreventsImplicitNullCheck()
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| D | MachinePipeliner.cpp | 1026 if (!TII->getMemOpBaseRegImmOfs(LdMI, BaseReg1, Offset1, TRI) || in addLoopCarriedDependences()
1027 !TII->getMemOpBaseRegImmOfs(MI, BaseReg2, Offset2, TRI)) { in addLoopCarriedDependences()
3024 if (!TII->getMemOpBaseRegImmOfs(MI, BaseReg, Offset, TRI)) in computeDelta()
3431 if (!TII->getMemOpBaseRegImmOfs(*SI, BaseRegS, OffsetS, TRI) || in isLoopCarriedOrder()
3432 !TII->getMemOpBaseRegImmOfs(*DI, BaseRegD, OffsetD, TRI)) in isLoopCarriedOrder()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrInfo.h | 219 bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 312 bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | ImplicitNullChecks.cpp | 365 if (!TII->getMemOpBaseRegImmOfs(MI, BaseReg, Offset, TRI) || in isSuitableMemoryOp()
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| D | MachinePipeliner.cpp | 1106 if (TII->getMemOpBaseRegImmOfs(LdMI, BaseReg1, Offset1, TRI) && in addLoopCarriedDependences()
1107 TII->getMemOpBaseRegImmOfs(MI, BaseReg2, Offset2, TRI)) { in addLoopCarriedDependences()
3148 if (!TII->getMemOpBaseRegImmOfs(MI, BaseReg, Offset, TRI)) in computeDelta()
3558 if (!TII->getMemOpBaseRegImmOfs(*SI, BaseRegS, OffsetS, TRI) || in isLoopCarriedDep()
3559 !TII->getMemOpBaseRegImmOfs(*DI, BaseRegD, OffsetD, TRI)) in isLoopCarriedDep()
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| D | MachineSink.cpp | 740 if (!TII->getMemOpBaseRegImmOfs(MI, BaseReg, Offset, TRI)) in SinkingPreventsImplicitNullCheck()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 329 bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
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| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.h | 113 bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
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| D | SIInstrInfo.cpp | 205 bool SIInstrInfo::getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, in getMemOpBaseRegImmOfs() function in SIInstrInfo
1346 if (getMemOpBaseRegImmOfs(MIa, BaseReg0, Offset0, &RI) && in checkInstOffsetsDoNotOverlap()
1347 getMemOpBaseRegImmOfs(MIb, BaseReg1, Offset1, &RI)) { in checkInstOffsetsDoNotOverlap()
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| D | SIMachineScheduler.cpp | 1819 if (SITII->getMemOpBaseRegImmOfs(*SU->getInstr(), BaseLatReg, OffLatReg, in schedule()
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 1021 virtual bool getMemOpBaseRegImmOfs(MachineInstr &MemOp, unsigned &BaseReg, in getMemOpBaseRegImmOfs() function
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| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | TargetInstrInfo.h | 1123 virtual bool getMemOpBaseRegImmOfs(MachineInstr &MemOp, unsigned &BaseReg, in getMemOpBaseRegImmOfs() function
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIInstrInfo.h | 163 bool getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg,
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| D | SIInstrInfo.cpp | 267 bool SIInstrInfo::getMemOpBaseRegImmOfs(MachineInstr &LdSt, unsigned &BaseReg, in getMemOpBaseRegImmOfs() function in SIInstrInfo
2123 if (getMemOpBaseRegImmOfs(MIa, BaseReg0, Offset0, &RI) && in checkInstOffsetsDoNotOverlap()
2124 getMemOpBaseRegImmOfs(MIb, BaseReg1, Offset1, &RI)) { in checkInstOffsetsDoNotOverlap()
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