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Searched refs:hasVSX (Results 1 – 20 of 20) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCTargetTransformInfo.cpp262 return ST->hasVSX() ? 64 : 32; in getNumberOfRegisters()
369 if (ST->hasVSX() && Val->getScalarType()->isDoubleTy()) { in getVectorInstrCost()
414 bool IsVSXType = ST->hasVSX() && in getMemoryOpCost()
424 if (Opcode == Instruction::Load && ST->hasVSX() && IsAltivecType && in getMemoryOpCost()
449 if (IsVSXType || (ST->hasVSX() && IsAltivecType)) in getMemoryOpCost()
DPPCSubtarget.h246 bool hasVSX() const { return HasVSX; } in hasVSX() function
293 return hasVSX() && isLittleEndian() && !hasP9Vector(); in needsSwapsForVSXMemOps()
DPPCVSXCopy.cpp150 if (!STI.hasVSX()) in runOnMachineFunction()
DPPCVSXFMAMutate.cpp352 if (!STI.hasVSX()) in runOnMachineFunction()
DPPCRegisterInfo.cpp139 if (Subtarget.hasVSX()) in getCalleeSavedRegs()
212 if (Subtarget.hasVSX()) in getCallPreservedMask()
383 if (Subtarget.hasVSX()) { in getLargestLegalSuperClass()
DPPCVSXSwapRemoval.cpp202 if (!STI.hasVSX() || !STI.needsSwapsForVSXMemOps()) in runOnMachineFunction()
DPPCISelLowering.cpp670 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) { in PPCTargetLowering()
697 if (Subtarget.hasVSX()) { in PPCTargetLowering()
3443 if (Subtarget.hasVSX()) in LowerFormalArguments_32SVR4()
3868 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() in LowerFormalArguments_64SVR4()
7897 if (Subtarget.hasVSX() && in LowerBUILD_VECTOR()
8407 if (Subtarget.hasVSX() && in LowerVECTOR_SHUFFLE()
8420 if (Subtarget.hasVSX() && in LowerVECTOR_SHUFFLE()
8453 if (Subtarget.hasVSX()) { in LowerVECTOR_SHUFFLE()
8769 if (Subtarget.hasVSX()) { in getVectorCompareInfo()
10828 (VT == MVT::v2f64 && Subtarget.hasVSX()) || in getSqrtEstimate()
[all …]
DPPCISelDAGToDAG.cpp3671 Opc = PPCSubTarget->hasVSX() ? PPC::XSCMPUDP : PPC::FCMPUD; in SelectCC()
3674 assert(PPCSubTarget->hasVSX() && "__float128 requires VSX"); in SelectCC()
3955 PPCSubTarget->hasVSX(), Swap, Negate); in trySETCC()
3962 CurDAG->SelectNodeTo(N, PPCSubTarget->hasVSX() ? PPC::XXLNOR : PPC::VNOR, in trySETCC()
4624 if (PPCSubTarget->hasVSX()) in Select()
4652 if (PPCSubTarget->hasVSX()) { in Select()
4660 if (PPCSubTarget->hasVSX() && (N->getValueType(0) == MVT::v2f64 || in Select()
DPPCInstrInfo.cpp1282 if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass) in loadRegFromStackSlot()
2137 assert(Subtarget.hasVSX() && in expandPostRAPseudo()
3109 if (Subtarget.hasVSX() && RC == &PPC::VRRCRegClass) in updatedRC()
DPPCInstrVSX.td115 def HasVSX : Predicate<"PPCSubTarget->hasVSX()">;
/external/llvm/lib/Target/PowerPC/
DPPCTargetTransformInfo.cpp224 return ST->hasVSX() ? 64 : 32; in getNumberOfRegisters()
320 if (ST->hasVSX() && Val->getScalarType()->isDoubleTy()) { in getVectorInstrCost()
370 bool IsVSXType = ST->hasVSX() && in getMemoryOpCost()
391 if (IsVSXType || (ST->hasVSX() && IsAltivecType)) in getMemoryOpCost()
DPPCCallingConv.td71 CCIfType<[v2f64, v2i64], CCIfSubtarget<"hasVSX()",
124 CCIfType<[v2f64, v2i64], CCIfSubtarget<"hasVSX()",
193 CCIfType<[v2f64, v2i64], CCIfSubtarget<"hasVSX()",
DPPCVSXCopy.cpp160 if (!STI.hasVSX()) in runOnMachineFunction()
DPPCSubtarget.h241 bool hasVSX() const { return HasVSX; } in hasVSX() function
DPPCRegisterInfo.cpp105 if (Subtarget.hasVSX()) in getCalleeSavedRegs()
164 if (Subtarget.hasVSX()) in getCallPreservedMask()
321 if (Subtarget.hasVSX()) { in getLargestLegalSuperClass()
DPPCVSXFMAMutate.cpp351 if (!STI.hasVSX()) in runOnMachineFunction()
DPPCISelDAGToDAG.cpp2084 Opc = PPCSubTarget->hasVSX() ? PPC::XSCMPUDP : PPC::FCMPUD; in SelectCC()
2364 PPCSubTarget->hasVSX(), Swap, Negate); in trySETCC()
2371 CurDAG->SelectNodeTo(N, PPCSubTarget->hasVSX() ? PPC::XXLNOR : PPC::VNOR, in trySETCC()
2836 if (PPCSubTarget->hasVSX()) in Select()
2858 if (PPCSubTarget->hasVSX()) { in Select()
2866 if (PPCSubTarget->hasVSX() && (N->getValueType(0) == MVT::v2f64 || in Select()
DPPCISelLowering.cpp532 if (TM.Options.UnsafeFPMath || Subtarget.hasVSX()) { in PPCTargetLowering()
559 if (Subtarget.hasVSX()) { in PPCTargetLowering()
2957 if (Subtarget.hasVSX()) in LowerFormalArguments_32SVR4()
3385 VReg = MF.addLiveIn(FPR[FPR_idx], Subtarget.hasVSX() in LowerFormalArguments_64SVR4()
7464 if (Subtarget.hasVSX()) { in LowerVECTOR_SHUFFLE()
7709 if (Subtarget.hasVSX()) { in getVectorCompareInfo()
9460 (VT == MVT::v2f64 && Subtarget.hasVSX()) || in getRsqrtEstimate()
9482 (VT == MVT::v2f64 && Subtarget.hasVSX()) || in getRecipEstimate()
10312 if (N->getValueType(0) != MVT::v2f64 || !Subtarget.hasVSX()) in DAGCombineBuildVector()
10636 if (Subtarget.hasVSX() && Subtarget.isLittleEndian() && in PerformDAGCombine()
[all …]
DPPCVSXSwapRemoval.cpp199 if (!STI.hasVSX()) in runOnMachineFunction()
DPPCInstrVSX.td92 def HasVSX : Predicate<"PPCSubTarget->hasVSX()">;