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Searched refs:isIntReg (Results 1 – 10 of 10) sorted by relevance

/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp194 if (HexagonMCInstrInfo::isIntReg(SrcReg) && in getDuplexCandidateGroup()
251 HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg && in getDuplexCandidateGroup()
319 if (HexagonMCInstrInfo::isIntReg(Src1Reg) && in getDuplexCandidateGroup()
365 HexagonMCInstrInfo::isIntReg(Src1Reg) && Hexagon::R29 == Src1Reg && in getDuplexCandidateGroup()
413 if (HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg && in getDuplexCandidateGroup()
DHexagonMCInstrInfo.h222 bool isIntReg(unsigned Reg);
DHexagonMCInstrInfo.cpp519 bool HexagonMCInstrInfo::isIntReg(unsigned Reg) { in isIntReg() function in llvm::HexagonMCInstrInfo
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCDuplexInfo.cpp202 if (HexagonMCInstrInfo::isIntReg(SrcReg) && in getDuplexCandidateGroup()
259 HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg && in getDuplexCandidateGroup()
321 if (HexagonMCInstrInfo::isIntReg(Src1Reg) && in getDuplexCandidateGroup()
367 HexagonMCInstrInfo::isIntReg(Src1Reg) && Hexagon::R29 == Src1Reg && in getDuplexCandidateGroup()
415 if (HexagonMCInstrInfo::isIntReg(SrcReg) && Hexagon::R29 == SrcReg && in getDuplexCandidateGroup()
DHexagonMCInstrInfo.h248 bool isIntReg(unsigned Reg);
DHexagonMCInstrInfo.cpp602 bool HexagonMCInstrInfo::isIntReg(unsigned Reg) { in isIntReg() function in HexagonMCInstrInfo
/external/llvm/lib/Target/Hexagon/
DHexagonExpandCondsets.cpp272 bool isIntReg(RegisterRef RR, unsigned &BW);
1098 bool HexagonExpandCondsets::isIntReg(RegisterRef RR, unsigned &BW) { in isIntReg() function in HexagonExpandCondsets
1135 if (!isIntReg(R1, BW1) || !isIntReg(R2, BW2) || BW1 != BW2) in coalesceRegisters()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonExpandCondsets.cpp235 bool isIntReg(RegisterRef RR, unsigned &BW);
1101 bool HexagonExpandCondsets::isIntReg(RegisterRef RR, unsigned &BW) { in isIntReg() function in HexagonExpandCondsets
1136 if (!isIntReg(R1, BW1) || !isIntReg(R2, BW2) || BW1 != BW2) in coalesceRegisters()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/AsmParser/
DSparcAsmParser.cpp260 bool isIntReg() const { in isIntReg() function in __anon132d2cec0211::SparcOperand
1281 if (Op.isIntReg() && Kind == MCK_IntPair) { in validateTargetOperandClass()
/external/llvm/lib/Target/Sparc/AsmParser/
DSparcAsmParser.cpp232 bool isIntReg() const { in isIntReg() function in __anoncba7d3b40111::SparcOperand
1293 if (Op.isIntReg() && Kind == MCK_IntPair) { in validateTargetOperandClass()