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Searched refs:isSpillable (Results 1 – 17 of 17) sorted by relevance

/external/llvm/lib/CodeGen/
DRegAllocBasic.cpp180 if (!Intf->isSpillable() || Intf->weight > VirtReg.weight) in spillInterferences()
259 if (!VirtReg.isSpillable()) in selectOrSplit()
DRegAllocGreedy.cpp765 bool Urgent = !VirtReg.isSpillable() && in canEvictInterference()
766 (Intf->isSpillable() || in canEvictInterference()
836 VirtReg.isSpillable() < Intf->isSpillable()) && in evictInterference()
2086 assert((getStage(VirtReg) >= RS_Done || !VirtReg.isSpillable()) && in tryLastChanceRecoloring()
2253 if (getStage(VirtReg) == RS_Spill && VirtReg.isSpillable()) { in tryAssignCSRFirstTime()
2536 if (Stage >= RS_Done || !VirtReg.isSpillable()) in selectOrSplitImpl()
DCalcSpillWeights.cpp149 bool Spillable = li.isSpillable(); in calculateSpillWeightAndHint()
DInlineSpiller.cpp1034 assert(edit.getParent().isSpillable() && in spill()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DRegAllocBasic.cpp217 if (!Intf->isSpillable() || Intf->weight > VirtReg.weight) in spillInterferences()
296 if (!VirtReg.isSpillable()) in selectOrSplit()
DLiveRangeEdit.cpp41 if (Parent && !Parent->isSpillable()) in createEmptyIntervalFrom()
66 if (Parent && !Parent->isSpillable()) in createFrom()
DRegAllocGreedy.cpp908 bool Urgent = !VirtReg.isSpillable() && in canEvictInterference()
909 (Intf->isSpillable() || in canEvictInterference()
1072 VirtReg.isSpillable() < Intf->isSpillable()) && in evictInterference()
2565 assert((getStage(VirtReg) >= RS_Done || !VirtReg.isSpillable()) && in tryLastChanceRecoloring()
2762 if (getStage(VirtReg) == RS_Spill && VirtReg.isSpillable()) { in tryAssignCSRFirstTime()
3062 if (Stage >= RS_Done || !VirtReg.isSpillable()) in selectOrSplitImpl()
DCalcSpillWeights.cpp174 bool Spillable = li.isSpillable(); in weightCalcHelper()
DInlineSpiller.cpp1089 assert(edit.getParent().isSpillable() && in spill()
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DRegAllocGreedy.cpp552 bool Urgent = !VirtReg.isSpillable() && Intf->isSpillable(); in canEvictInterference()
600 VirtReg.isSpillable() < Intf->isSpillable()) && in evictInterference()
1586 if (Stage >= RS_Done || !VirtReg.isSpillable()) in selectOrSplit()
DCalcSpillWeights.cpp107 bool Spillable = li.isSpillable(); in CalculateWeightAndHint()
DRegAllocBasic.cpp525 if (!VirtReg.isSpillable()) in selectOrSplit()
DInlineSpiller.cpp1265 assert(edit.getParent().isSpillable() && in spill()
DLiveIntervalAnalysis.cpp1743 assert(li.isSpillable() && "attempt to spill already spilled interval!"); in addIntervalsForSpills()
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DLiveInterval.h512 bool isSpillable() const {
/external/llvm/include/llvm/CodeGen/
DLiveInterval.h723 bool isSpillable() const { in isSpillable() function
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DLiveInterval.h767 bool isSpillable() const { in isSpillable() function