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/external/swiftshader/third_party/llvm-7.0/llvm/docs/
DAMDGPUAsmGFX7.rst691 … dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
692 … dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
693 v_add_i32_e64 dst0, dst1, src0, src1 :ref:`omod<amdgpu_synid_omod>`
694 v_addc_u32_e64 dst0, dst1, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
695 v_alignbit_b32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
696 v_alignbyte_b32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
697 v_and_b32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
698 v_ashr_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
699 v_ashr_i64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
700 v_ashrrev_i32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
[all …]
DAMDGPUAsmGFX9.rst745 …v_bfrev_b32_sdwa dst, src0 :ref:`omod<amdgpu_synid_omod>` :ref:…
748 … dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`…
751 … dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`…
756 … dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`…
759 … dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`…
762 … dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`…
765 … dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`…
768 … dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`…
771 … dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`…
775 … dst, src0 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`…
[all …]
DAMDGPUAsmGFX8.rst936 … dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
937 … dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
938 … dst, src0, src1 :ref:`clamp<amdgpu_synid_clamp>` :ref:`omod<amdgpu_synid_omod>`
939 v_add_u16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
940 v_add_u32_e64 dst0, dst1, src0, src1 :ref:`omod<amdgpu_synid_omod>`
941 v_addc_u32_e64 dst0, dst1, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
942 v_alignbit_b32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
943 v_alignbyte_b32 dst, src0, src1, src2 :ref:`omod<amdgpu_synid_omod>`
944 v_and_b32_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
945 v_ashrrev_i16_e64 dst, src0, src1 :ref:`omod<amdgpu_synid_omod>`
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Domod.ll95 ; Clamp is applied after omod, folding both into instruction is OK.
108 ; Cannot fold omod into clamp
187 ; Don't fold omod into omod into another omod.
199 ; Don't fold omod if denorms enabled
210 ; Don't fold omod if denorms enabled for add form.
221 ; Don't fold omod if denorms enabled
232 ; Don't fold omod if denorms enabled for add form.
Dclamp-omod-special-case.mir127 # Don't fold a mul that looks like an omod if itself has omod set
191 # Don't fold a mul that looks like an omod if itself has clamp set
269 # Don't fold a mul that looks like an omod if itself has omod set
333 # Don't fold a mul that looks like an omod if itself has clamp set
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DVOP3Instructions.td16 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
138 let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod" in {
150 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
229 clampmod:$clamp, omod:$omod);
231 let Asm64 = "$vdst, $src0_modifiers, $attr$attrchan$clamp$omod";
237 clampmod:$clamp, omod:$omod);
239 let Asm64 = "$vdst, $src0, $attr$attrchan$clamp$omod";
246 string omod = !if(HasOMod, "$omod", "");
248 " $vdst, $src0_modifiers, $attr$attrchan"#src2#"$high$clamp"#omod;
258 highmod:$high, clampmod:$clamp, omod:$omod),
[all …]
DR600InstrFormats.td138 bits<2> omod;
145 let Word1{6-5} = omod;
200 let Inst{39-38} = omod;
208 let Inst{38-37} = omod;
DVOPInstructions.td177 bits<2> omod;
187 let Inst{60-59} = !if(P.HasOMod, omod, 0);
248 bits<2> omod;
256 let Inst{60-59} = !if(P.HasOMod, omod, 0);
384 bits<2> omod;
389 let Inst{47-46} = !if(P.HasSDWAOMod, omod{1-0}, 0);
DVOP1Instructions.td92 i1:$clamp, i32:$omod))))],
95 i1:$clamp, i32:$omod))))],
113 let Ins64 = (ins Src0RC64:$src0, clampmod:$clamp, omod:$omod);
114 let Asm64 = "$vdst, $src0$clamp$omod";
264 clampmod:$clamp, omod:$omod, dst_sel:$dst_sel, dst_unused:$dst_unused,
DSIInstrInfo.td740 def omod : NamedOperandU32<"OModSI", NamedMatchClass<"OModSI">>;
1263 clampmod:$clamp, omod:$omod)
1276 clampmod:$clamp, omod:$omod),
1294 clampmod:$clamp, omod:$omod),
1424 // VOP1_SDWA without omod
1429 // VOP1_SDWA with omod
1431 clampmod:$clamp, omod:$omod,
1442 // VOP2_SDWA without omod
1448 // VOP2_SDWA with omod
1451 clampmod:$clamp, omod:$omod,
[all …]
DSIFoldOperands.cpp789 if (TII->hasModifiersSet(MI, AMDGPU::OpName::omod)) in isClamp()
910 TII->hasModifiersSet(MI, AMDGPU::OpName::omod) || in isOMod()
932 !TII->hasModifiersSet(MI, AMDGPU::OpName::omod)) in isOMod()
953 MachineOperand *DefOMod = TII->getNamedOperand(*Def, AMDGPU::OpName::omod); in tryFoldOMod()
DSIPeepholeSDWA.cpp871 if (!ST.hasSDWAOmod() && TII->hasModifiersSet(MI, AMDGPU::OpName::omod)) in isConvertibleToSDWA()
883 TII->hasModifiersSet(MI, AMDGPU::OpName::omod))) in isConvertibleToSDWA()
983 if (AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::omod) != -1) { in convertToSDWA()
984 MachineOperand *OMod = TII->getNamedOperand(MI, AMDGPU::OpName::omod); in convertToSDWA()
DSIShrinkInstructions.cpp116 return !TII->hasModifiersSet(MI, AMDGPU::OpName::omod) && in canShrink()
/external/mesa3d/src/gallium/drivers/r600/sb/
Dsb_expr.cpp337 if (bc.omod) in apply_alu_dst_mod()
338 v = v.f * omod_coeff[bc.omod - 1]; in apply_alu_dst_mod()
369 if (b0.clamp != b1.clamp || b0.omod != b1.omod) in ops_equal()
403 if (!sd->bc.clamp && !sd->bc.omod && !sd->bc.src[0].abs && in fold_alu_op1()
413 && n.bc.clamp == 0 && n.bc.omod == 0 in fold_alu_op1()
493 !n->bc.src[1].abs && !n->bc.src[0].abs && !d0->bc.omod && in fold_mul_add()
494 !d0->bc.clamp && !n->bc.omod && in fold_mul_add()
530 !n->bc.src[0].abs && !n->bc.src[1].abs && !d1->bc.omod && in fold_mul_add()
531 !d1->bc.clamp && !n->bc.omod && in fold_mul_add()
660 !d0->bc.omod && !d0->bc.clamp && in fold_assoc()
[all …]
Dsb_bc_builder.cpp430 .OMOD(bc.omod) in build_alu()
447 .OMOD(bc.omod) in build_alu()
461 .EXECUTE_MASK_OP(bc.omod) in build_alu()
476 .OMOD(bc.omod) in build_alu()
Dsb_dump.cpp411 if (n->bc.omod) { in dump_alu()
413 sblog << omod_str[n->bc.omod]; in dump_alu()
Dsb_peephole.cpp238 if (d->bc.omod) in optimize_CNDcc_op()
Dsb_bc_decoder.cpp372 bc.omod = w1.get_OMOD(); in decode_alu()
391 bc.omod = w1.get_OMOD(); in decode_alu()
/external/llvm/lib/Target/AMDGPU/
DVIInstrFormats.td123 bits<2> omod;
134 let Inst{60-59} = omod;
163 bits<2> omod;
174 let Inst{60-59} = omod;
DR600InstrFormats.td128 bits<2> omod;
135 let Word1{6-5} = omod;
190 let Inst{39-38} = omod;
198 let Inst{38-37} = omod;
DSIInstrInfo.td547 def omod : NamedOperandU32<"OModSI", NamedMatchClass<"OModSI">>;
1209 clampmod:$clamp, omod:$omod)
1219 clampmod:$clamp, omod:$omod)
1230 clampmod:$clamp, omod:$omod)
1351 dst#", "#src0#src1#src2#"$clamp"#"$omod");
1545 let Asm64 = "$vdst, $sdst, $src0_modifiers, $src1_modifiers, $src2_modifiers"#"$clamp"#"$omod";
1847 bits<2> omod = !if(HasModifiers, ?, 0);
1860 bits<2> omod = !if(HasOutputMods, ?, 0);
2115 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
2127 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
[all …]
DSIInstrFormats.td406 bits<2> omod;
417 let Inst{60-59} = omod;
446 bits<2> omod;
455 let Inst{60-59} = omod;
DSIShrinkInstructions.cpp119 if (TII->hasModifiersSet(MI, AMDGPU::OpName::omod)) in canShrink()
/external/mesa3d/src/gallium/drivers/r600/
Dr700_asm.c71 S_SQ_ALU_WORD1_OP2_OMOD(alu->omod) | in r700_bytecode_alu_build()
120 alu->omod = G_SQ_ALU_WORD1_OP2_OMOD(word1); in r700_bytecode_alu_read()
Dr600_asm.h62 unsigned omod; member

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