| /external/u-boot/arch/arm/dts/ |
| D | stm32f429.dtsi | 47 #include <dt-bindings/mfd/stm32f4-rcc.h>
81 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
90 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
110 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
119 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
139 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
148 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
168 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
176 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
196 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
[all …]
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| D | stm32f746.dtsi | 51 #include <dt-bindings/mfd/stm32f7-rcc.h>
68 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(ETHMAC)>,
69 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACTX)>,
70 <&rcc 0 STM32F7_AHB1_CLOCK(ETHMACRX)>;
82 clocks = <&rcc 0 STM32F7_AHB3_CLOCK(FMC)>;
94 clocks = <&rcc 0 STM32F7_AHB3_CLOCK(QSPI)>;
95 resets = <&rcc STM32F7_AHB3_RESET(QSPI)>;
102 clocks = <&rcc 0 STM32F7_APB2_CLOCK(USART1)>;
112 rcc: rcc@40023810 { label
115 compatible = "st,stm32f746-rcc", "st,stm32-rcc";
[all …]
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| D | stm32h743.dtsi | 46 #include <dt-bindings/mfd/stm32h7-rcc.h>
70 rcc: rcc@58024400 { label
73 compatible = "st,stm32h743-rcc", "st,stm32-rcc";
84 clocks = <&rcc USART1_CK>;
92 clocks = <&rcc USART2_CK>;
99 clocks = <&rcc TIM5_CK>;
110 clocks = <&rcc FMC_CK>;
129 clocks = <&rcc SDMMC1_CK>;
130 resets = <&rcc STM32H7_AHB3_RESET(SDMMC1)>;
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| D | stm32h743-pinctrl.dtsi | 59 clocks = <&rcc GPIOA_CK>;
68 clocks = <&rcc GPIOB_CK>;
77 clocks = <&rcc GPIOC_CK>;
86 clocks = <&rcc GPIOD_CK>;
95 clocks = <&rcc GPIOE_CK>;
104 clocks = <&rcc GPIOF_CK>;
113 clocks = <&rcc GPIOG_CK>;
122 clocks = <&rcc GPIOH_CK>;
131 clocks = <&rcc GPIOI_CK>;
140 clocks = <&rcc GPIOJ_CK>;
[all …]
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| D | stm32mp157.dtsi | 103 rcc: rcc@50000000 { label
108 rcc_clk: rcc-clk@50000000 {
110 compatible = "st,stm32mp1-rcc-clk";
113 rcc_rst: rcc-reset@50000000 {
115 compatible = "st,stm32mp1-rcc-rst";
118 rcc_reboot: rcc-reboot@50000000 {
120 regmap = <&rcc>;
131 st,sysrcc = <&rcc>;
137 st,tzcr = <&rcc 0x0 0x1>;
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| D | stm32f4-pinctrl.dtsi | 45 #include <dt-bindings/mfd/stm32f4-rcc.h>
63 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
73 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
83 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
93 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
103 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
113 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
123 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
133 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
143 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
[all …]
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| D | stm32f469-disco.dts | 85 &rcc {
86 compatible = "st,stm32f469-rcc", "st,stm32f42xx-rcc", "st,stm32-rcc";
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| D | stm32f429-disco.dts | 107 assigned-clocks = <&rcc 1 CLK_RTC>;
108 assigned-clock-parents = <&rcc 1 CLK_LSI>;
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| D | stm32f429-disco-u-boot.dtsi | 37 clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>;
85 &rcc {
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| D | stm32429i-eval-u-boot.dtsi | 37 clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>;
90 &rcc {
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| D | stm32f469-disco-u-boot.dtsi | 37 clocks = <&rcc 0 STM32F4_AHB3_CLOCK(FMC)>;
90 &rcc {
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| D | stm32h7-u-boot.dtsi | 30 &rcc {
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| D | stm32mp157-u-boot.dtsi | 62 &rcc {
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| D | stm32429i-eval.dts | 93 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHSULPI)>;
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| /external/u-boot/drivers/clk/ |
| D | clk_stm32mp1.c | 1105 static void stm32mp1_ls_osc_set(int enable, fdt_addr_t rcc, u32 offset, in stm32mp1_ls_osc_set() argument
1108 u32 address = rcc + offset; in stm32mp1_ls_osc_set()
1116 static void stm32mp1_hs_ocs_set(int enable, fdt_addr_t rcc, u32 mask_on) in stm32mp1_hs_ocs_set() argument
1119 setbits_le32(rcc + RCC_OCENSETR, mask_on); in stm32mp1_hs_ocs_set()
1121 setbits_le32(rcc + RCC_OCENCLRR, mask_on); in stm32mp1_hs_ocs_set()
1124 static int stm32mp1_osc_wait(int enable, fdt_addr_t rcc, u32 offset, in stm32mp1_osc_wait() argument
1128 u32 address = rcc + offset; in stm32mp1_osc_wait()
1146 static void stm32mp1_lse_enable(fdt_addr_t rcc, int bypass, int lsedrv) in stm32mp1_lse_enable() argument
1151 setbits_le32(rcc + RCC_BDCR, RCC_BDCR_LSEBYP); in stm32mp1_lse_enable()
1157 value = (readl(rcc + RCC_BDCR) & RCC_BDCR_LSEDRV_MASK) in stm32mp1_lse_enable()
[all …]
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| /external/u-boot/doc/device-tree-bindings/clock/ |
| D | st,stm32-rcc.txt | 11 "st,stm32f42xx-rcc"
12 "st,stm32f469-rcc"
23 rcc: rcc@40023800 {
26 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
46 - include/dt-bindings/mfd/stm32f4-rcc.h
52 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>
57 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)>
74 clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)>
94 resets = <&rcc STM32F4_APB1_RESET(TIM2)>;
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| D | st,stm32h7-rcc.txt | 11 "st,stm32h743-rcc"
33 rcc: rcc@58024400 {
36 compatible = "st,stm32h743-rcc", "st,stm32-rcc";
127 clocks = <&rcc TIM5_CK>;
145 All available preprocessor macros for reset are defined dt-bindings//mfd/stm32h7-rcc.h
151 resets = <&rcc STM32H7_APB1L_RESET(TIM2)>;
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| D | st,stm32mp1.txt | 8 RCC CLOCK = st,stm32mp1-rcc-clk
15 Please refer to ../mfd/st,stm32-rcc.txt for all the other properties common
20 - compatible: Should be "st,stm32mp1-rcc-clk"
96 rcc: rcc@50000000 {
101 rcc_clk: rcc-clk@50000000 {
103 compatible = "st,stm32mp1-rcc-clk";
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| /external/u-boot/drivers/ram/stm32mp1/ |
| D | stm32mp1_ddr.c | 383 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST); in stm32mp1_ddr_init()
384 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST); in stm32mp1_ddr_init()
385 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST); in stm32mp1_ddr_init()
386 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST); in stm32mp1_ddr_init()
387 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST); in stm32mp1_ddr_init()
388 setbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST); in stm32mp1_ddr_init()
397 clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST); in stm32mp1_ddr_init()
398 clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST); in stm32mp1_ddr_init()
402 clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST); in stm32mp1_ddr_init()
428 clrbits_le32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST); in stm32mp1_ddr_init()
[all …]
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| D | stm32mp1_ram.c | 156 priv->rcc = STM32_RCC_BASE; in stm32mp1_ddr_probe()
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| D | stm32mp1_ddr.h | 37 u32 rcc; member
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| /external/u-boot/doc/device-tree-bindings/reset/ |
| D | st,stm32-rcc.txt | 6 Please see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt
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| /external/u-boot/doc/device-tree-bindings/regulator/ |
| D | st,stm32-vrefbuf.txt | 19 clocks = <&rcc VREF_CK>;
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| /external/u-boot/doc/device-tree-bindings/i2c/ |
| D | i2c-stm32.txt | 23 resets = <&rcc 181>;
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| /external/u-boot/doc/device-tree-bindings/ram/ |
| D | st,stm32-fmc.txt | 34 clocks = <&rcc 0 64>;
|