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Searched refs:s_load_dwordx4 (Results 1 – 25 of 63) sorted by relevance

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/external/llvm/test/MC/AMDGPU/
Dout-of-range-registers.s25 s_load_dwordx4 s[102:105], s[2:3], s4 label
28 s_load_dwordx4 s[104:108], s[2:3], s4 label
31 s_load_dwordx4 s[108:112], s[2:3], s4 label
34 s_load_dwordx4 s[1:4], s[2:3], s4 label
37 s_load_dwordx4 s[1:4], s[2:3], s4 label
Dsmrd.s47 s_load_dwordx4 s[4:7], s[2:3], 1 label
51 s_load_dwordx4 s[4:7], s[2:3], s4 label
55 s_load_dwordx4 ttmp[4:7], ttmp[2:3], ttmp4 label
59 s_load_dwordx4 s[100:103], s[2:3], s4 label
Dsmrd-err.s4 s_load_dwordx4 s[100:103], s[2:3], s4 label
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/
Dout-of-range-registers.s25 s_load_dwordx4 s[102:105], s[2:3], s4 label
28 s_load_dwordx4 s[104:108], s[2:3], s4 label
31 s_load_dwordx4 s[108:112], s[2:3], s4 label
34 s_load_dwordx4 s[1:4], s[2:3], s4 label
37 s_load_dwordx4 s[1:4], s[2:3], s4 label
Dsmrd.s94 s_load_dwordx4 s[4:7], s[2:3], 1 label
98 s_load_dwordx4 s[4:7], s[2:3], s4 label
102 s_load_dwordx4 ttmp[4:7], ttmp[2:3], ttmp4 label
106 s_load_dwordx4 s[100:103], s[2:3], s4 label
Dsmrd-err.s4 s_load_dwordx4 s[100:103], s[2:3], s4 label
Dsym_kernel_scope.s53 s_load_dwordx4 s[D:D+3], s[E:E+1], 0x0
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dkernel-args.ll279 ; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0xd
280 ; MESA-VI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x34
281 ; HSA-VI: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x10
294 ; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0xd
295 ; MESA-VI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x34
296 ; HSA-VI: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x10
353 ; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xd
354 ; MESA-VI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x34
355 ; HSA-VI: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[4:5], 0x10
369 ; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xd
[all …]
Dinline-constraints.ll13 ; GCN: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}]
14 ; GCN: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}]
27 …%s4_32 = tail call <4 x i32> asm sideeffect "s_load_dwordx4 $0, $1", "=s,s"(i32 addrspace(1)* %pt…
28 %s128 = tail call i128 asm sideeffect "s_load_dwordx4 $0, $1", "=s,s"(i32 addrspace(1)* %ptr)
Dconstant-address-space-32bit.ll44 ; SICI-DAG: s_load_dwordx4 s[{{.*}}], s[0:1], 0x0
45 ; SICI-DAG: s_load_dwordx4 s[{{.*}}], s[2:3], 0x8
46 ; VIGFX9-DAG: s_load_dwordx4 s[{{.*}}], s[0:1], 0x0
47 ; VIGFX9-DAG: s_load_dwordx4 s[{{.*}}], s[2:3], 0x20
127 ; SICI-DAG: s_load_dwordx4 s[{{.*}}], s[0:1], 0x0
128 ; SICI-DAG: s_load_dwordx4 s[{{.*}}], s[2:3], 0x8
129 ; VIGFX9-DAG: s_load_dwordx4 s[{{.*}}], s[0:1], 0x0
130 ; VIGFX9-DAG: s_load_dwordx4 s[{{.*}}], s[2:3], 0x20
208 ; GCN-NEXT: s_load_dwordx4
242 ; GCN-NEXT: s_load_dwordx4
Dwait.ll8 ; DEFAULT: s_load_dwordx4
9 ; DEFAULT: s_load_dwordx4
39 ; ILPMAX: s_load_dwordx4
42 ; ILPMAX: s_load_dwordx4
Damdpal.ll17 ; PAL: s_load_dwordx4 s{{\[}}[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s{{\[}}[[GITPTR]]:
41 ; PAL: s_load_dwordx4 s{{\[}}[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s{{\[}}[[GITPTR]]:
62 ; PAL: s_load_dwordx4 s{{\[}}[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s{{\[}}[[GITPTR]]:{{[0-9]+\]}}, 0x…
Dreduce-store-width-alignment.ll13 ; GCN: s_load_dwordx4
32 ; GCN: s_load_dwordx4
Dany_extend_vector_inreg.ll5 ; GCN: s_load_dwordx4
6 ; GCN-DAG: s_load_dwordx4
Dschedule-kernel-arg-loads.ll5 ; SI: s_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x9
8 ; VI: s_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x24
Dmemory_clause.ll40 ; GCN-NEXT: s_load_dwordx4
41 ; GCN-NEXT: s_load_dwordx4
42 ; GCN-NEXT: s_load_dwordx4
43 ; GCN-NEXT: s_load_dwordx4
Dload-constant-i32.ll29 ; GCN: s_load_dwordx4
40 ; GCN: s_load_dwordx4
154 ; GCN: s_load_dwordx4
166 ; GCN: s_load_dwordx4
/external/llvm/test/CodeGen/AMDGPU/
Dwait.ll8 ; DEFAULT: s_load_dwordx4
9 ; DEFAULT: s_load_dwordx4
38 ; ILPMAX: s_load_dwordx4
41 ; ILPMAX: s_load_dwordx4
Dinline-constraints.ll10 ; GCN: s_load_dwordx4 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}]
20 …%s128 = tail call <4 x i32> asm sideeffect "s_load_dwordx4 $0, $1", "=s,s"(i32 addrspace(1)* %ptr)
Dreduce-store-width-alignment.ll13 ; GCN: s_load_dwordx4
32 ; GCN: s_load_dwordx4
Dkernel-args.ll167 ; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0xd
168 ; VI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x34
179 ; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0xd
180 ; VI: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x34
222 ; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xd
223 ; VI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x34
235 ; SI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0xd
236 ; VI: s_load_dwordx4 s{{\[[0-9]:[0-9]\]}}, s[0:1], 0x34
Dload-constant-i32.ll29 ; GCN: s_load_dwordx4
40 ; GCN: s_load_dwordx4
154 ; GCN: s_load_dwordx4
166 ; GCN: s_load_dwordx4
/external/swiftshader/third_party/llvm-7.0/llvm/test/Object/AMDGPU/
Dobjdump.s35 s_load_dwordx4 s[8:11], s[4:5], 0x40
/external/llvm/test/Object/AMDGPU/
Dobjdump.s32 s_load_dwordx4 s[8:11], s[4:5], 0x40
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/
Dsmrd_vi.txt24 # VI: s_load_dwordx4 s[4:7], s[2:3], 0x1 ; encoding: [0x01,0x01,0x0a,0xc0,0x01,0x00,0x00,0x00]
27 # VI: s_load_dwordx4 s[4:7], s[2:3], s4 ; encoding: [0x01,0x01,0x08,0xc0,0x04,0x00,0x00,0x00]

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