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/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86RegisterInfo.td1 //===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
213 // Floating point stack registers. These don't map one-to-one to the FP
279 // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
284 // 64-bit mode. The main complication is that they cannot be encoded in an
394 // mode to prevent encoding using the 0x90 NOP encoding. xchg %eax, %eax needs
DX86InstrCompiler.td1 //===- X86InstrCompiler.td - Compiler Pseudos and Patterns -*- tablegen -*-===//
91 (ins i8mem:$ap, i32imm:$size, i8imm:$mode, i32imm:$align),
92 "#VAARG_64 $dst, $ap, $size, $mode, $align",
94 (X86vaarg64 addr:$ap, imm:$size, imm:$mode, imm:$align)),
156 // Alias instructions that map movr0 to xor.
860 // code model mode, should use 'movabs'. FIXME: This is really a hack, the
901 // If we have small model and -static mode, it is safe to store global addresses
953 // FIXME: This is disabled for 32-bit PIC mode because the global base
954 // register which is part of the address mode may be assigned a
DX86InstrSSE.td1 //====- X86InstrSSE.td - Describe the X86 Instruction Set --*- tablegen -*-===//
241 // Alias instructions that map fld0 to pxor for sse.
2822 // only in OptForSize mode. It eliminates an instruction, but it also
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrFormats.td1 //===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===//
140 // Class specifying the opcode map.
162 // Operand size for encodings that change based on mode.
167 def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode.
168 def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode.
170 // Address size for encodings that change based on mode.
213 // part of W1X. This would probably simplify the tablegen emitters and
282 // based on operand size of the mode?
285 // based on address size of the mode?
290 Map OpMap = OB; // Which opcode map does this inst have?
[all …]
DX86RegisterInfo.td1 //===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
277 // Floating point stack registers. These don't map one-to-one to the FP
371 // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
376 // 64-bit mode. The main complication is that they cannot be encoded in an
DX86InstrAVX512.td1 //===-- X86InstrAVX512.td - AVX512 Instruction Set ---------*- tablegen -*-===//
145 // We map scalar types to the smallest (128-bit) vector type
482 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
6673 // 213 and 231 patterns this helps tablegen's duplicate pattern detection.
6681 // 213 and 231 patterns this helps tablegen's duplicate pattern detection.
6805 // 213 and 231 patterns this helps tablegen's duplicate pattern detection.
6972 // Patterns with rounding mode.
7060 // This enables commuted load patterns to be autogenerated by tablegen.
8468 // rounding mode (Nearest-Even, encoded as 0). Both are equivalent in the
DX86InstrSSE.td1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
110 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
7494 // rounding mode (Nearest-Even, encoded as 0). Both are equivalent in the
/external/llvm/lib/Target/X86/
DX86RegisterInfo.td1 //===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
238 // Floating point stack registers. These don't map one-to-one to the FP
319 // In 64-mode, there are 12 additional i8 registers, SIL, DIL, BPL, SPL, and
324 // 64-bit mode. The main complication is that they cannot be encoded in an
399 // mode to prevent encoding using the 0x90 NOP encoding. xchg %eax, %eax needs
DX86InstrFormats.td1 //===-- X86InstrFormats.td - X86 Instruction Formats -------*- tablegen -*-===//
124 // Class specifying the opcode map.
145 // Operand size for encodings that change based on mode.
150 def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode.
151 def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode.
153 // Address size for encodings that change based on mode.
249 // based on operand size of the mode?
252 // based on address size of the mode?
257 Map OpMap = OB; // Which opcode map does this inst have?
918 // MMXI32 - MMX instructions with TB prefix valid only in 32 bit mode.
[all …]
DX86InstrSSE.td1 //===-- X86InstrSSE.td - SSE Instruction Set ---------------*- tablegen -*-===//
451 // Alias instructions that map fld0 to xorps for sse or vxorps for avx.
8229 // rounding mode (Nearest-Even, encoded as 0). Both are equivalent in the
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/
DTarget.td1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
25 // A string representing subtarget features that turn on this HW mode.
26 // For example, "+feat1,-feat2" will indicate that the mode is active
34 // A special mode recognized by tablegen. This mode is considered active
35 // when no other mode is active. For targets that do not use specific hw
36 // modes, this is the only mode.
49 // dependent on a HW mode. This class inherits from ValueType itself,
67 // The register size/alignment information, parameterized by a HW mode.
160 // is invalid for this mode/flavour.
211 // The register size/alignment information, parameterized by a HW mode.
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/docs/
DGlobalISel.rst207 There are four required passes, regardless of the optimization mode:
378 lookups though, encoding a map from the integers (i.e. the size of the current
462 We intend to eventually introduce an additional optimizing mode:
468 On AArch64, we are considering using the Greedy mode even at -O0 (or perhaps at
525 ``-gen-globalisel`` tablegen command from ``ninja -v`` and modify it.
/external/clang/docs/
DInternalsManual.rst110 you to map almost any diagnostic to the output level that you want. The only
430 mentioned, the diagnostic machinery goes through some filtering to map a
444 mode. Instead of formatting and printing out the diagnostics, this
448 documentation for the ``-verify`` mode can be found in the Clang API
522 To map from this representation to a character-based representation, the "last"
599 not reading in "raw" mode) this contains a pointer to the unique hash value
731 * The lexer can operate in "raw" mode. This mode has several features that
734 This mode is used for lexing within an "``#if 0``" block, for example.
736 support the ``-C`` preprocessor mode, which passes comments through, and is
738 * The lexer can be in ``ParsingFilename`` mode, which happens when
[all …]
/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTarget.td1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
80 // is invalid for this mode/flavour.
252 // is invalid for this mode/flavour.
387 /// Which instruction it expands to and how the operands map from the
790 // verbose-asm mode). These two values indicate the width of the first column
792 // verbose asm mode is enabled, operands will be indented to respect this.
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrInfo.td1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
333 AssemblerPredicate<"!ModeThumb", "arm-mode">;
493 // Operands that are part of a memory addressing mode.
504 // Branches targeting ARM-mode must be divisible by 4 if they're a raw
510 // Branches targeting Thumb-mode must be divisible by 2 if they're a raw
530 // Target for BLX *from* ARM mode.
1970 /// mode). Used mostly in ARM and Thumb-1 modes.
2072 bits<5> mode;
2078 let Inst{17} = M; // Enabled if mode is set;
2082 let Inst{4-0} = mode;
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DARMInstrThumb2.td1 //===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===//
1376 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1509 // pseudos map between the two.
1532 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1617 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
2083 // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
3679 bits<5> mode;
3686 let Inst{4-0} = mode;
3691 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3692 "$imod\t$iflags, $mode">;
[all …]
/external/llvm/lib/Target/ARM/
DARMInstrInfo.td1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
291 AssemblerPredicate<"!ModeThumb", "arm-mode">;
410 // Operands that are part of a memory addressing mode.
421 // Branches targeting ARM-mode must be divisible by 4 if they're a raw
427 // Branches targeting Thumb-mode must be divisible by 2 if they're a raw
447 // Target for BLX *from* ARM mode.
1866 /// mode). Used mostly in ARM and Thumb-1 modes.
1965 bits<5> mode;
1971 let Inst{17} = M; // Enabled if mode is set;
1975 let Inst{4-0} = mode;
[all …]
DARMInstrThumb2.td1 //===-- ARMInstrThumb2.td - Thumb2 support for ARM ---------*- tablegen -*-===//
1385 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1508 // pseudos map between the two.
1528 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1611 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
2043 // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
3693 bits<5> mode;
3700 let Inst{4-0} = mode;
3705 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3706 "$imod\t$iflags, $mode">;
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/
DMBlazeInstrInfo.td1 //===- MBlazeInstrInfo.td - MBlaze Instruction defs --------*- tablegen -*-===//
409 // MBlaze immediate mode arithmetic instructions
723 // Arbitrary patterns that map to one or more instructions
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoV4.td1 //=- HexagonInstrInfoV4.td - Target Desc. for Hexagon Target -*- tablegen -*-=//
392 // Template class for load instructions with Absolute set addressing mode.
536 // base + register offset addressing mode
560 // base + register offset addressing mode
595 // addressing mode
684 // Template class for store instructions with Absolute set addressing mode.
853 // base + register offset addressing mode
882 // base + register offset addressing mode
920 // base + register offset addressing mode
946 // base + register offset addressing mode
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrInfo.td1 //===- ARMInstrInfo.td - Target Description for ARM Target -*- tablegen -*-===//
1648 bits<5> mode;
1654 let Inst{17} = M; // Enabled if mode is set;
1658 let Inst{4-0} = mode;
1663 def CPS3p : CPS<(ins imod_op:$imod, iflags_op:$iflags, imm0_31:$mode),
1664 "$imod\t$iflags, $mode">;
1665 let mode = 0, M = 0 in
1669 def CPS1p : CPS<(ins imm0_31:$mode), "\t$mode">;
1735 // Address computation and loads and stores in PIC mode.
2070 : XI<(outs), (ins imm0_31:$mode), AddrModeNone, 4, IndexModeNone, BrFrm,
[all …]
DARMInstrThumb2.td1283 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110).
1381 // pseudos map between the two.
1402 // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly
1459 // instr_write is inverted for Thumb mode: (prefetch 3) -> (preload 0),
1837 // FIXME: Eliminate t2ADDS/t2SUBS pseudo opcodes after adding tablegen
3275 bits<5> mode;
3287 let Inst{4-0} = mode;
3292 def t2CPS3p : t2CPS<(ins imod_op:$imod, iflags_op:$iflags, i32imm:$mode),
3293 "$imod.w\t$iflags, $mode">;
3294 let mode = 0, M = 0 in
[all …]
/external/llvm/include/llvm/Target/
DTarget.td1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
110 // is invalid for this mode/flavour.
301 // is invalid for this mode/flavour.
497 /// Which instruction it expands to and how the operands map from the
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td1 //=- AArch64InstrInfo.td - Describe the AArch64 Instructions -*- tablegen -*-=//
1360 // Thus, it is safe to directly map the vector loads with interesting
1528 // Thus, it is safe to directly map the vector loads with interesting
1797 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't
1970 // FIXME: Use dedicated range-checked addressing mode operand here.
5390 // In big endian mode every memory access has an implicit byte swap. LDR and
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64InstrInfo.td1 //=- AArch64InstrInfo.td - Describe the AArch64 Instructions -*- tablegen -*-=//
1567 // Thus, it is safe to directly map the vector loads with interesting
1735 // Thus, it is safe to directly map the vector loads with interesting
2004 // the don't otherwise match the scaled addressing mode for LDR/STR. Don't
2177 // FIXME: Use dedicated range-checked addressing mode operand here.
5782 // In big endian mode every memory access has an implicit byte swap. LDR and