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/external/libavc/common/armv8/
Dih264_weighted_bi_pred_av8.s203 ld1 {v12.8b}, [x0], x3 //load row 3 in source 1
212 uxtl v12.8h, v12.8b //converting row 3 in source 1 to 16-bit
218 mul v12.8h, v12.8h , v2.h[0] //weight 1 mult. for row 3
219 mla v12.8h, v14.8h , v2.h[2] //weight 2 mult. for row 3
224 srshl v12.8h, v12.8h , v0.8h //rounds off the weighted samples from row 3
228 saddw v12.8h, v12.8h , v3.8b //adding offset for row 3
232 sqxtun v12.8b, v12.8h //saturating row 3 to unsigned 8-bit
237 st1 {v12.8b}, [x2], x5 //store row 3 in destination
249 ld1 {v12.8b, v13.8b}, [x0], x3 //load row 3 in source 1
266 uxtl v28.8h, v12.8b //converting row 3L in source 1 to 16-bit
[all …]
Dih264_inter_pred_luma_horz_qpel_vert_qpel_av8.s187 ld1 {v12.2s, v13.2s}, [x7], x2 // src[6_0]
195 uaddl v16.8h, v2.8b, v12.8b
248 umlsl v16.8h, v12.8b, v31.8b
293 umlal v0.8h, v12.8b, v30.8b
345 mov v4.16b, v12.16b
391 ld1 {v12.2s, v13.2s}, [x7], x2 // src[10_0]
397 uaddl v16.8h, v2.8b, v12.8b
448 umlsl v16.8h, v12.8b, v31.8b
493 umlal v0.8h, v12.8b, v30.8b
545 mov v4.16b, v12.16b
[all …]
Dih264_inter_pred_filters_luma_vert_av8.s135 uaddl v12.8h, v4.8b, v6.8b // temp1 = src[2_0] + src[3_0]
142 mla v14.8h, v12.8h, v22.8h // temp += temp1 * 20
148 uaddl v12.8h, v6.8b, v8.8b
152 mla v16.8h, v12.8h , v22.8h
155 uaddl v12.8h, v7.8b, v9.8b
159 mla v14.8h, v12.8h , v22.8h
163 uaddl v12.8h, v8.8b, v10.8b
166 mla v18.8h, v12.8h , v22.8h
170 uaddl v12.8h, v9.8b, v11.8b
173 mla v16.8h, v12.8h , v22.8h
[all …]
Dih264_inter_pred_luma_vert_qpel_av8.s142 uaddl v12.8h, v4.8b, v6.8b // temp1 = src[2_0] + src[3_0]
149 mla v14.8h, v12.8h , v22.8h // temp += temp1 * 20
155 uaddl v12.8h, v6.8b, v8.8b
159 mla v16.8h, v12.8h , v22.8h
162 uaddl v12.8h, v7.8b, v9.8b
166 mla v14.8h, v12.8h , v22.8h
173 uaddl v12.8h, v8.8b, v10.8b
175 mla v18.8h, v12.8h , v22.8h
179 uaddl v12.8h, v9.8b, v11.8b
182 mla v16.8h, v12.8h , v22.8h
[all …]
Dih264_inter_pred_luma_horz_qpel_vert_hpel_av8.s160 ld1 {v12.2s}, [x0], x2 // Vector load from src[0_0]
186 uaddl v22.8h, v12.8b, v17.8b
255 ld1 {v12.2s}, [x0], x2 // Vector load from src[6_0]
273 uaddl v22.8h, v13.8b, v12.8b
359 uaddl v26.8h, v15.8b, v12.8b
442 uaddl v24.8h, v17.8b, v12.8b
507 mov v14.16b, v12.16b
527 mov v12.16b, v16.16b
552 uaddl v12.8h, v0.8b, v10.8b
554 mla v12.8h, v14.8h , v26.8h
[all …]
Dih264_inter_pred_luma_horz_hpel_vert_hpel_av8.s99 ld1 {v12.2s}, [x0], x2 // Vector load from src[0_0]
124 uaddl v22.8h, v12.8b, v17.8b
187 ld1 {v12.2s}, [x0], x2 // Vector load from src[6_0]
205 uaddl v22.8h, v13.8b, v12.8b
286 uaddl v26.8h, v15.8b, v12.8b
364 uaddl v24.8h, v17.8b, v12.8b
428 mov v14.16b, v12.16b
444 mov v12.16b, v16.16b
467 uaddl v12.8h, v0.8b, v10.8b
469 mla v12.8h, v14.8h , v26.8h
[all …]
Dih264_deblk_luma_av8.s101 mov v12.s[0], w4 //d12[0] = ui_Bs
106 uxtl v12.8h, v12.8b //q6 = uc_Bs in each 16 bt scalar
119 tbl v14.8b, {v16.16b}, v12.8b //
123 uxtl v12.4s, v12.4h //
127 cmgt v12.4s, v12.4s, #0
143 bic v12.16b, v12.16b , v18.16b //final condition
153 and v20.16b, v20.16b , v12.16b //
154 and v22.16b, v22.16b , v12.16b //
163 … and v18.16b, v18.16b , v12.16b //Making delta zero in places where values shouldn be filterd
265 uabd v12.16b , v4.16b, v6.16b
[all …]
Dih264_deblk_chroma_av8.s228 uabd v12.16b, v0.16b , v2.16b //|p1-p0|
233 cmhi v12.16b, v24.16b , v12.16b //|p1-p0| < beta ?
245 and v8.16b, v8.16b , v12.16b //|p0-q0| < alpha && |q1-q0| < beta && |p1-p0| < beta
341 mov v12.s[0], w6 //D12[0] = ui_Bs
345 tbl v14.8b, {v16.16b}, v12.8b //Retreiving cliptab values for U
346 tbl v28.8b, {v17.16b}, v12.8b //Retrieving cliptab values for V
347 uxtl v12.8h, v12.8b //Q6 = uc_Bs in each 16 bit scalar
383 cmgt v12.4h, v12.4h, #0
393 mov v13.8b, v12.8b
394 mov v12.d[1], v13.d[0] //
[all …]
Dih264_iquant_itrans_recon_av8.s183 sub v12.4h, v5.4h , v6.4h // x1-x2
193 trn1 v6.4h, v12.4h, v13.4h
194 trn2 v7.4h, v12.4h, v13.4h
198 trn2 v12.2s, v4.2s, v6.2s // 4
205 add v14.4h, v10.4h, v12.4h // x0 = q0 + q2//
206 sub v15.4h, v10.4h, v12.4h // x1 = q0 - q2//
372 sub v12.4h, v5.4h , v6.4h // x1-x2
384 trn1 v6.4h, v12.4h, v13.4h
385 trn2 v7.4h, v12.4h, v13.4h
389 trn2 v12.2s, v4.2s, v6.2s // 4
[all …]
Dih264_intra_pred_luma_8x8_av8.s327 add v12.8h, v8.8h , v10.8h
328 sqrshrun v31.8b, v12.8h, #4
347 uaddlp v12.1d, v13.2s
348 rshrn v4.8b, v12.8h, #3
696 ext v12.16b, v16.16b , v16.16b , #1
701 st1 {v12.h}[5], [x1], #2
719 st1 {v12.s}[2], [x1], #4
815 mov v12.16b, v8.16b
818 trn1 v13.8h, v12.8h, v14.8h
819 trn2 v14.8h, v12.8h, v14.8h
[all …]
Dih264_inter_pred_luma_horz_hpel_vert_qpel_av8.s194 uaddl v12.8h, v2.8b, v3.8b
199 mla v10.8h, v12.8h , v22.8h
201 uaddl v12.8h, v1.8b, v4.8b
203 mls v10.8h, v12.8h , v24.8h
205 uaddl v12.8h, v0.8b, v5.8b
213 mla v12.8h, v14.8h , v22.8h
217 mls v12.8h, v14.8h , v24.8h
224 st1 {v12.4s}, [x9], x6 // store temp buffer 3
248 add v30.8h, v10.8h , v12.8h
278 add v30.8h, v12.8h , v14.8h
[all …]
Dih264_iquant_itrans_recon_dc_av8.s250 ld1 {v12.d}[0], [x2], x4
251 ld1 {v12.d}[1], [x2]
266 bit v12.16b, v2.16b, v31.16b
270 st1 {v12.d}[0], [x0], x4
271 st1 {v12.d}[1], [x0]
380 uaddw v12.8h, v0.8h, v29.8b
389 sqxtun v12.8b, v12.8h
398 st1 {v12.8b}, [x2]
Dih264_intra_pred_chroma_av8.s272 dup v12.8h, v0.h[5]
278 st1 {v12.8h}, [x1], x3
437 usubl v12.8h, v3.8b, v7.8b
439 mul v16.8h, v12.8h , v8.8h
460 rshrn v12.4h, v24.4s, #6
474 dup v4.8h, v12.h[0]
498 mul v12.8h, v4.8h , v8.8h
500 add v12.8h, v0.8h , v12.8h
508 add v24.8h, v12.8h , v4.8h
510 add v2.8h, v12.8h , v14.8h
[all …]
Dih264_inter_pred_luma_horz_qpel_av8.s183 ld1 {v12.2s, v13.2s}, [x7], x2 //Load value for interpolation (column1,row0)
188 urhadd v20.16b, v12.16b , v20.16b //Interpolation step for qpel calculation
199 ld1 {v12.2s, v13.2s}, [x7], x2 //Load value for interpolation (column1,row1)
201 urhadd v18.16b, v12.16b , v18.16b //Interpolation step for qpel calculation
244 ld1 {v12.2s, v13.2s}, [x7], x2 //Load value for interpolation (column1,row2)
249 urhadd v20.16b, v12.16b , v20.16b //Interpolation step for qpel calculation
256 ld1 {v12.2s, v13.2s}, [x7], x2 //Load value for interpolation (column1,row3)
260 urhadd v18.16b, v12.16b , v18.16b //Interpolation step for qpel calculation
302 ld1 {v12.2s, v13.2s}, [x7], x2 //Load value for interpolation (column1,row4)
307 urhadd v20.16b, v12.16b , v20.16b //Interpolation step for qpel calculation
[all …]
/external/libhevc/common/arm64/
Dihevc_intra_pred_chroma_planar.s187 umull v12.8h, v5.8b, v0.8b //(row+1) * src[nt-1]
190 umlal v12.8h, v6.8b, v10.8b //(nt-1-row) * src[2nt+1+col]
192 umlal v12.8h, v17.8b, v1.8b //(col+1) * src[3nt+1]
194 umlal v12.8h, v30.8b, v4.8b //(nt-1-col) * src[2nt-1-row]
211 add v12.8h, v12.8h , v16.8h //add (nt)
213 sshl v12.8h, v12.8h, v14.8h //shr
228 xtn v12.8b, v12.8h
239 st1 {v12.2s, v13.2s}, [x2], x3
257 umull v12.8h, v18.8b, v0.8b //(row+1) * src[nt-1]
259 umlal v12.8h, v19.8b, v10.8b //(nt-1-row) * src[2nt+1+col]
[all …]
Dihevc_itrans_recon_32x32.s242 ld1 {v12.4h},[x0],x6
265 smlal v20.4s, v12.4h, v1.h[0]
267 smlal v22.4s, v12.4h, v3.h[0]
269 smlal v16.4s, v12.4h, v5.h[0]
271 smlal v18.4s, v12.4h, v7.h[0]
314 ld1 {v12.4h},[x0],x6
339 smlal v20.4s, v12.4h, v3.h[0]
341 smlsl v22.4s, v12.4h, v7.h[0]
343 smlsl v16.4s, v12.4h, v1.h[0]
345 smlsl v18.4s, v12.4h, v5.h[0]
[all …]
Dihevc_itrans_recon_8x8.s201 ld1 {v12.4h},[x0],x5
296 movi v12.4h, #0
367 smull v22.4s, v12.4h, v0.h[0] //// y4 * cos4(part of c0 and c1)
377 add v12.4s, v20.4s , v22.4s //// c0 = y0 * cos4 + y4 * cos4(part of a0 and a1)
385 add v16.4s, v12.4s , v8.4s //// a0 = c0 + d0(part of e0,e7)
386 sub v12.4s, v12.4s , v8.4s //// a3 = c0 - d0(part of e3,e4)
399 add v26.4s, v12.4s , v30.4s //// a3 + b3(part of e3)
400 sub v30.4s, v12.4s , v30.4s //// a3 - b3(part of x4)
409 sqrshrn v12.4h, v30.4s,#shift_stage1_idct //// x4 = (a3 - b3 + rnd) >> 7(shift_stage1_idct)
561 add v12.4s, v20.4s , v14.4s //// a0 = c0 + d0(part of x0,x7)
[all …]
/external/libxaac/decoder/armv8/
Dixheaacd_cos_sin_mod_loop2.s112 add v12.2d, v8.2d , v6.2d
120 ST1 {v12.s}[0], [x3], x8
124 SQNEG v12.4s, v12.4s
127 ST1 {v12.s}[2], [x10], #4
152 add v12.2d, v8.2d , v6.2d
160 ST1 {v12.s}[0], [x0], #4
162 SQNEG v12.4s, v12.4s
164 ST1 {v12.s}[2], [x11], x8
191 add v12.2d, v4.2d , v10.2d
199 ST1 {v12.s}[0], [x3], x8
[all …]
Dixheaacd_imdct_using_fft.s207 LD2 {v12.S, v13.S}[0], [X5] , X1
217 LD2 {v12.S, v13.S}[1], [X6] , X1
226 LD2 {v12.S, v13.S}[2], [X7] , X1
235 LD2 {v12.S, v13.S}[3], [X11] , X1
250 ADD v17.4S, v14.4S, v12.4S
254 SUB v16.4S, v14.4S, v12.4S
262 SUB v12.4S, v15.4S, v13.4S
274 ADD v14.4S, v16.4S, v12.4S
275 SUB v10.4S, v16.4S, v12.4S
277 SUB v12.4S, v13.4S, v1.4S
[all …]
Dixheaacd_inv_dit_fft_8pt.s62 SQADD v12.2s, v4.2s, v8.2s //a30_v = vqadd_s32(y5_7,y13_15);
70 SQADD v7.2s, v10.2s, v12.2s //x1_9 = vqadd_s32(a20_v,a30_v);
73 SQSUB v8.2s, v10.2s, v12.2s //x5_13 = vqsub_s32(a20_v,a30_v);
90 SQADD v12.2s, v6.2s, v7.2s //real_imag4 = vqadd_s32(x4_5,x13_12);
94 MOV w4, v12.s[1]
95 MOV v12.s[1], v14.s[1]
153 ST1 {v12.s}[0], [x1], #4
160 ST1 {v12.s}[1], [x2], #4
/external/libmpeg2/common/armv8/
Dimpeg2_idct.s176 uaddw v12.8h, v30.8h , v2.8b
181 sqxtun v2.8b, v12.8h
242 raddhn v12.4h, v0.4s, v8.4s
243 raddhn2 v12.8h, v0.4s, v10.4s
244 uaddw v14.8h, v12.8h , v30.8b
252 raddhn v12.4h, v0.4s, v8.4s
253 raddhn2 v12.8h, v0.4s, v10.4s
254 uaddw v14.8h, v12.8h , v30.8b
262 raddhn v12.4h, v0.4s, v8.4s
263 raddhn2 v12.8h, v0.4s, v10.4s
[all …]
/external/llvm/test/MC/Disassembler/AMDGPU/
Dvop1.txt90 # CHECK: v_sqrt_f32_e32 v123, v12 ; encoding: [0x0c,0x4f,0xf6,0x7e]
93 # CHECK: v_sin_f32_e32 v123, v12 ; encoding: [0x0c,0x53,0xf6,0x7e]
96 # CHECK: v_cos_f32_e32 v123, v12 ; encoding: [0x0c,0x55,0xf6,0x7e]
99 # CHECK: v_not_b32_e32 v123, v12 ; encoding: [0x0c,0x57,0xf6,0x7e]
102 # CHECK: v_bfrev_b32_e32 v123, v12 ; encoding: [0x0c,0x59,0xf6,0x7e]
105 # CHECK: v_ffbh_u32_e32 v123, v12 ; encoding: [0x0c,0x5b,0xf6,0x7e]
108 # CHECK: v_ffbl_b32_e32 v123, v12 ; encoding: [0x0c,0x5d,0xf6,0x7e]
111 # CHECK: v_ffbh_i32_e32 v123, v12 ; encoding: [0x0c,0x5f,0xf6,0x7e]
138 # CHECK: v_cvt_off_f32_i4_e32 v123, v12 ; encoding: [0x0c,0x1d,0xf6,0x7e]
141 # CHECK: v_cvt_f32_ubyte0_e32 v123, v12 ; encoding: [0x0c,0x23,0xf6,0x7e]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/
Dvop1.txt90 # CHECK: v_sqrt_f32_e32 v123, v12 ; encoding: [0x0c,0x4f,0xf6,0x7e]
93 # CHECK: v_sin_f32_e32 v123, v12 ; encoding: [0x0c,0x53,0xf6,0x7e]
96 # CHECK: v_cos_f32_e32 v123, v12 ; encoding: [0x0c,0x55,0xf6,0x7e]
99 # CHECK: v_not_b32_e32 v123, v12 ; encoding: [0x0c,0x57,0xf6,0x7e]
102 # CHECK: v_bfrev_b32_e32 v123, v12 ; encoding: [0x0c,0x59,0xf6,0x7e]
105 # CHECK: v_ffbh_u32_e32 v123, v12 ; encoding: [0x0c,0x5b,0xf6,0x7e]
108 # CHECK: v_ffbl_b32_e32 v123, v12 ; encoding: [0x0c,0x5d,0xf6,0x7e]
111 # CHECK: v_ffbh_i32_e32 v123, v12 ; encoding: [0x0c,0x5f,0xf6,0x7e]
138 # CHECK: v_cvt_off_f32_i4_e32 v123, v12 ; encoding: [0x0c,0x1d,0xf6,0x7e]
141 # CHECK: v_cvt_f32_ubyte0_e32 v123, v12 ; encoding: [0x0c,0x23,0xf6,0x7e]
[all …]
/external/libhevc/decoder/arm64/
Dihevcd_fmt_conv_420sp_to_rgba8888.s206 sMULL v12.4s, v4.4h, v0.h[1] ////(U-128)*C2 FOR G
207 sMLAL v12.4s, v6.4h, v0.h[2] ////Q6 = (U-128)*C2 + (V-128)*C3
222 sqshrn v12.4h, v12.4s,#13 ////D12 = [(U-128)*C2 + (V-128)*C3]>>13 4 16-BIT VALUES
223 sqshrn2 v12.8h, v14.4s,#13 ////D13 = [(U-128)*C2 + (V-128)*C3]>>13 4 16-BIT VALUES
228 UADDW v18.8h, v12.8h , v30.8b ////Q9 - HAS Y + G
232 UADDW v24.8h, v12.8h , v31.8b ////Q12 - HAS Y + G
284 UADDW v18.8h, v12.8h , v28.8b ////Q3 - HAS Y + G
288 UADDW v24.8h, v12.8h , v29.8b ////Q12 - HAS Y + G
369 sMULL v12.4s, v4.4h, v0.h[1] ////(U-128)*C2 FOR G
370 sMLAL v12.4s, v6.4h, v0.h[2] ////Q6 = (U-128)*C2 + (V-128)*C3
[all …]
/external/vixl/test/test-trace-reference/
Dlog-vregs13 # v12: 0x403570fb41385373403025ae416d0626
40 # v12: 0x000000000000000000000000ffffffff
64 # v12: 0x0000000000000000000000000000ffff
65 # v12: 0x00000000000000000000000000000000 (s12: 0.00000)
72 # v12: 0x00000000000000000000000000000012
83 # v12: 0x00000000000000000000000000000001
96 # v12: 0x00000000000000000000000000000000 (d12: 0.00000)
97 # v12: 0x00000000000000000000000000000000 (s12: 0.00000)
204 # v12: 0x0000000000000000000037000000bbfe
207 # v12: 0x00000000000000000000000000000000
[all …]

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