| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/ |
| D | vop-err.s | 156 v_addc_u32 v0, vcc, s0, v0, vcc label
159 v_addc_u32 v0, vcc, flat_scratch_lo, v0, vcc label
162 v_addc_u32 v0, vcc, flat_scratch_hi, v0, vcc label
165 v_addc_u32 v0, vcc, exec_lo, v0, vcc label
168 v_addc_u32 v0, vcc, exec_hi, v0, vcc label
|
| D | vop2.s | 331 v_addc_u32 v1, vcc, v2, v3, vcc label
340 v_addc_u32 v1, s[0:1], v2, v3, vcc label
344 v_addc_u32 v1, s[0:1], v2, v3, s[2:3] label
|
| D | vop2-err.s | 65 v_addc_u32 v1, s[0:1], v2, v3, 123 label
|
| D | vop_dpp.s | 549 v_addc_u32 v1, vcc, v2, v3, vcc row_shl:1 row_mask:0xa bank_mask:0x1 bound_ctrl:0 label
|
| D | gfx7_asm_all.s | 38946 v_addc_u32 v5, vcc, v1, v2, vcc label
38949 v_addc_u32 v255, vcc, v1, v2, vcc label
38952 v_addc_u32 v5, vcc, v255, v2, vcc label
38955 v_addc_u32 v5, vcc, 0, v2, vcc label
38958 v_addc_u32 v5, vcc, -1, v2, vcc label
38961 v_addc_u32 v5, vcc, 0.5, v2, vcc label
38964 v_addc_u32 v5, vcc, -4.0, v2, vcc label
38967 v_addc_u32 v5, vcc, v1, v255, vcc label
|
| D | gfx8_asm_all.s | 39648 v_addc_u32 v5, vcc, v1, v2, vcc label
39651 v_addc_u32 v255, vcc, v1, v2, vcc label
39654 v_addc_u32 v5, vcc, v255, v2, vcc label
39657 v_addc_u32 v5, vcc, 0, v2, vcc label
39660 v_addc_u32 v5, vcc, -1, v2, vcc label
39663 v_addc_u32 v5, vcc, 0.5, v2, vcc label
39666 v_addc_u32 v5, vcc, -4.0, v2, vcc label
39669 v_addc_u32 v5, vcc, v1, v255, vcc label
|
| /external/llvm/test/CodeGen/AMDGPU/ |
| D | add_i64.ll | 8 ; SI: v_addc_u32
23 ; SI: v_addc_u32
36 ; SI: v_addc_u32
58 ; SI: v_addc_u32
60 ; SI: v_addc_u32
|
| D | saddo.ll | 53 ; SI: v_addc_u32
|
| D | uaddo.ll | 72 ; SI: v_addc_u32
|
| D | split-scalar-i64-add.ll | 37 ; SI: v_addc_u32
|
| D | add.ll | 139 ; The v_addc_u32 and v_add_i32 instruction can't read SGPRs, because they
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
| D | add_i64.ll | 8 ; SI: v_addc_u32
58 ; SI: v_addc_u32
60 ; SI: v_addc_u32
|
| D | mad_64_32.ll | 10 ; SI: v_addc_u32
25 ; SI: v_addc_u32
40 ; SI: v_addc_u32
55 ; SI: v_addc_u32
|
| D | split-scalar-i64-add.ll | 40 ; SI: v_addc_u32
|
| D | add.ll | 168 ; The v_addc_u32 and v_add_i32 instruction can't read SGPRs, because they
|
| /external/llvm/test/MC/AMDGPU/ |
| D | vop2.s | 323 v_addc_u32 v1, vcc, v2, v3, vcc label
332 v_addc_u32 v1, s[0:1], v2, v3, vcc label
336 v_addc_u32 v1, s[0:1], v2, v3, s[2:3] label
|
| D | vop2-err.s | 65 v_addc_u32 v1, s[0:1], v2, v3, 123 label
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | VOP2Instructions.td | 398 defm V_ADDC_U32 : VOP2bInst <"v_addc_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_addc_u32", 1>;
887 defm V_ADDC_U32 : VOP2be_Real_e32e64_vi_only <0x1c, "V_ADDC_U32", "v_addc_u32">;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
| D | AMDGPUAsmGFX7.rst | 637 v_addc_u32 dst0, dst1, src0, src1, src2
|
| D | AMDGPUAsmGFX8.rst | 794 v_addc_u32 dst0, dst1, src0, src1, src2
|
| D | AMDGPUUsage.rst | 4278 v_addc_u32 v1, s[0:1], v2, v3, s[2:3]
|
| /external/llvm/lib/Target/AMDGPU/ |
| D | SIInstructions.td | 1577 defm V_ADDC_U32 : VOP2bInst <vop2<0x28, 0x1c>, "v_addc_u32",
|