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Searched refs:v_readlane_b32 (Results 1 – 25 of 31) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dpartial-sgpr-to-vgpr-spills.ll177 ; GCN: v_readlane_b32 s[[USE_TMP_LO:[0-9]+]], v0, 0
178 ; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 1
179 ; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 2
180 ; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 3
181 ; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 4
182 ; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 5
183 ; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v0, 6
184 ; GCN-NEXT: v_readlane_b32 s[[USE_TMP_HI:[0-9]+]], v0, 7
188 ; GCN: v_readlane_b32 s[[USE_TMP_LO]], v1, 0
189 ; GCN-NEXT: v_readlane_b32 s{{[0-9]+}}, v1, 1
[all …]
Dspill-wide-sgpr.ll24 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
25 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
65 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
66 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
67 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
68 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 3
122 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
123 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
124 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 2
125 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 3
[all …]
Dllvm.amdgcn.readlane.ll6 ; CHECK: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, s{{[0-9]+}}
15 ; CHECK: v_readlane_b32 s{{[0-9]+}}, [[VVAL]], s{{[0-9]+}}
24 ; CHECK: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, [[LANE]]
41 ; CHECK: v_readlane_b32 s{{[0-9]+}}, [[VVAL]], s{{[0-9]+}}
50 ; CHECK: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 32
Dcallee-frame-setup.ll53 ; GCN-DAG: v_readlane_b32 s35,
54 ; GCN-DAG: v_readlane_b32 s34,
55 ; GCN-DAG: v_readlane_b32 s33,
82 ; GCN-DAG: v_readlane_b32 s34, v32, 1
83 ; GCN-DAG: v_readlane_b32 s33, v32, 0
100 ; GCN: v_readlane_b32 s{{[0-9]+}}, v32
Dcall-preserved-registers.ll42 ; GCN: v_readlane_b32 s37, v32, 4
43 ; GCN: v_readlane_b32 s36, v32, 3
44 ; GCN: v_readlane_b32 s35, v32, 2
45 ; GCN: v_readlane_b32 s34, v32, 1
46 ; GCN: v_readlane_b32 s33, v32, 0
177 ; GCN-NEXT: v_readlane_b32 s33, v0, 0
205 ; GCN: v_readlane_b32 s40, v32
237 ; GCN: v_readlane_b32 s40, v33
Dnested-calls.ll22 ; GCN: v_readlane_b32 s35, v32, 2
23 ; GCN: v_readlane_b32 s34, v32, 1
24 ; GCN: v_readlane_b32 s33, v32, 0
Dcontrol-flow-fastregalloc.ll55 ; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_LO_LANE]]
56 ; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_HI_LANE]]
134 ; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_LO_LANE]]
135 ; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_HI_LANE]]
203 ; VGPR: v_readlane_b32 s[[FLOW_S_RELOAD_SAVEEXEC_LO:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_LO_LANE]]
204 ; VGPR: v_readlane_b32 s[[FLOW_S_RELOAD_SAVEEXEC_HI:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_HI_LANE]]
251 ; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], [[SPILL_VGPR]], [[FLOW_SAVEEXEC_LO_LANE]]
252 ; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], [[SPILL_VGPR]], [[FLOW_SAVEEXEC_HI_LANE]]
Dbasic-branch.ll11 ; GCNNOOPT: v_readlane_b32
12 ; GCNNOOPT: v_readlane_b32
Dbyval-frame-setup.ll49 ; GCN: v_readlane_b32
50 ; GCN-NOT: v_readlane_b32 s32
104 ; GCN-NOT: v_readlane_b32 s32
105 ; GCN: v_readlane_b32
106 ; GCN-NOT: v_readlane_b32 s32
Dcall-graph-register-usage.ll20 ; GCN: v_readlane_b32 s35, v32, 2
21 ; GCN: v_readlane_b32 s34, v32, 1
22 ; GCN: v_readlane_b32 s33, v32, 0
Dsibling-call.ll106 ; GCN-NOT: v_readlane_b32 s32
226 ; GCN-DAG: v_readlane_b32 s33, v34, 0
227 ; GCN-DAG: v_readlane_b32 s34, v34, 1
228 ; GCN-DAG: v_readlane_b32 s35, v34, 2
Dspill-csr-frame-ptr-reg-copy.ll10 ; GCN: v_readlane_b32 s5, v32, 2
Dspill-m0.ll30 ; TOVGPR: v_readlane_b32 [[M0_RESTORE:s[0-9]+]], [[SPILL_VREG]], 0
87 ; GCN-NOT: v_readlane_b32 m0
136 ; GCN-NOT: v_readlane_b32 m0
Dsi-spill-cf.ll8 ; SI-NOT: v_readlane_b32 [[SAVED]]
/external/llvm/test/CodeGen/AMDGPU/
Dbasic-branch.ll13 ; GCNNOOPT: v_readlane_b32
14 ; GCNNOOPT: v_readlane_b32
Dm0-spill.ll7 ; CHECK-NOT: v_readlane_b32 m0
Dsi-spill-cf.ll8 ; SI-NOT: v_readlane_b32 [[SAVED]]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/
Dvop2.s117 v_readlane_b32 s1, v2, s3 label
Dgfx7_asm_all.s31668 v_readlane_b32 s5, v1, s2 label
31671 v_readlane_b32 s103, v1, s2 label
31674 v_readlane_b32 tba_lo, v1, s2 label
31677 v_readlane_b32 tba_hi, v1, s2 label
31680 v_readlane_b32 tma_lo, v1, s2 label
31683 v_readlane_b32 tma_hi, v1, s2 label
31686 v_readlane_b32 ttmp11, v1, s2 label
31689 v_readlane_b32 s5, v255, s2 label
31692 v_readlane_b32 s5, v1, s103 label
31695 v_readlane_b32 s5, v1, flat_scratch_lo label
[all …]
/external/llvm/test/MC/AMDGPU/
Dvop2.s117 v_readlane_b32 s1, v2, s3 label
/external/llvm/test/MC/Disassembler/AMDGPU/
Dvop2_vi.txt6 # VI: v_readlane_b32 s1, v2, s3 ; encoding: [0x01,0x00,0x89,0xd2,0x02,0x07,0x00,0x00]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/
Dvop2_vi.txt6 # VI: v_readlane_b32 s1, v2, s3 ; encoding: [0x01,0x00,0x89,0xd2,0x02,0x07,0x00,0x00]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DVOP2Instructions.td413 def V_READLANE_B32 : VOP2_Pseudo<"v_readlane_b32", VOP_READLANE,
DSIInstructions.td505 // You cannot use M0 as the output of v_readlane_b32 instructions or
/external/llvm/lib/Target/AMDGPU/
DSIInstructions.td1594 "v_readlane_b32",
1597 "v_readlane_b32 $vdst, $src0, $src1"
2080 // It's unclear whether you can use M0 as the output of v_readlane_b32

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