| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 1233 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) in printVectorList() local
1235 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) in printVectorList() local
1237 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0)) in printVectorList() local
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/SelectionDAG/ |
| D | FunctionLoweringInfo.cpp | 223 unsigned FirstReg = 0; in CreateRegs() local
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | FunctionLoweringInfo.cpp | 373 unsigned FirstReg = 0; in CreateRegs() local
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | FunctionLoweringInfo.cpp | 382 unsigned FirstReg = 0; in CreateRegs() local
|
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| D | AArch64InstPrinter.cpp | 1307 if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0)) in printVectorList() local
1309 else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0)) in printVectorList() local
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.cpp | 494 unsigned FirstReg = 0; in ScanInstruction() local
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.cpp | 506 unsigned FirstReg = 0; in ScanInstruction() local
|
| /external/llvm/lib/CodeGen/ |
| D | AggressiveAntiDepBreaker.cpp | 487 unsigned FirstReg = 0; in ScanInstruction() local
|
| /external/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 1202 unsigned FirstReg = FirstRegs[NumRegs - 1]; in addVectorList64Operands() local
1215 unsigned FirstReg = FirstRegs[NumRegs - 1]; in addVectorList128Operands() local
2979 int64_t FirstReg = tryMatchVectorRegister(Kind, true); in parseVectorList() local
4616 int FirstReg = tryParseRegister(); in tryParseGPRSeqPair() local
|
| /external/capstone/arch/AArch64/ |
| D | AArch64InstPrinter.c | 1104 unsigned NumRegs = 1, FirstReg, i; in printVectorList() local
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 2096 unsigned &FirstReg, in CanFormLdStDWord()
2263 unsigned FirstReg = 0, SecondReg = 0; in RescheduleOps() local
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 2057 unsigned &FirstReg, in CanFormLdStDWord()
2217 unsigned FirstReg = 0, SecondReg = 0; in RescheduleOps() local
|
| D | ARMBaseInstrInfo.cpp | 2072 unsigned FirstReg = MI->getOperand(RegListIdx).getReg(); in tryFoldSPUpdateIntoPushPop() local
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 4028 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, in copyByValRegs()
4081 MachineFrameInfo &MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, in passByValArg()
4228 unsigned FirstReg = 0; in HandleByVal() local
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 3724 unsigned FirstReg, unsigned LastReg, const CCValAssign &VA, in copyByValRegs()
3773 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, unsigned FirstReg, in passByValArg()
3922 unsigned FirstReg = 0; in HandleByVal() local
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 791 unsigned FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect() local
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/AsmParser/ |
| D | AArch64AsmParser.cpp | 1495 unsigned FirstReg = FirstRegs[(unsigned)RegTy][NumRegs]; in addVectorListOperands() local
3191 unsigned FirstReg; in tryParseVectorList() local
5405 unsigned FirstReg; in tryParseGPRSeqPair() local
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3291 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadImmReal() local
4115 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandTrunc() local
4838 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandLoadStoreDMacro() local
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceTargetLoweringMIPS32.cpp | 1935 const auto FirstReg = in legalizeMov() local
2007 const auto FirstReg = in legalizeMov() local
2094 const auto FirstReg = in legalizeMov() local
|
| D | IceTargetLoweringARM32.cpp | 406 const auto FirstReg = in copyRegAllocFromInfWeightVariable64On32() local
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.cpp | 843 unsigned FirstReg = SwapOps ? FalseReg : TrueReg, in insertSelect() local
|
| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 3139 unsigned FirstReg = Inst.getOperand(0).getReg(); in expandTrunc() local
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 3707 unsigned FirstReg = Reg; in parseVectorList() local
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 3992 unsigned FirstReg = Reg; in parseVectorList() local
|