| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/SVE/ |
| D | lsl.s | 10 lsl z0.b, z0.b, #0 label
16 lsl z31.b, z31.b, #7 label
22 lsl z0.h, z0.h, #0 label
28 lsl z31.h, z31.h, #15 label
34 lsl z0.s, z0.s, #0 label
40 lsl z31.s, z31.s, #31 label
46 lsl z0.d, z0.d, #0 label
52 lsl z31.d, z31.d, #63 label
58 lsl z0.b, p0/m, z0.b, #0 label
64 lsl z31.b, p0/m, z31.b, #7 label
[all …]
|
| D | lsl-diagnostics.s | 3 lsl z18.b, z28.b, #-1 label
8 lsl z1.b, z9.b, #8 label
13 lsl z18.b, p0/m, z28.b, #-1 label
18 lsl z1.b, p0/m, z9.b, #8 label
23 lsl z21.h, z2.h, #-1 label
28 lsl z14.h, z30.h, #16 label
33 lsl z21.h, p0/m, z2.h, #-1 label
38 lsl z14.h, p0/m, z30.h, #16 label
43 lsl z6.s, z12.s, #-1 label
48 lsl z23.s, z19.s, #32 label
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/X86/ |
| D | intel-syntax.s | 875 lsl rbx, word ptr [eax] label
878 lsl ebx, word ptr [eax] label
881 lsl bx, word ptr [eax] label
|
| /external/arm-optimized-routines/math/single/ |
| D | e_powf.c | 464 float a, ax, sh, sl, lsh, lsl; in powf() local
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAddressingModes.h | 29 lsl, enumerator
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAddressingModes.h | 30 lsl, enumerator
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMAddressingModes.h | 30 lsl, enumerator
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 812 void lsl(const Register& rd, const Register& rn, unsigned shift) { in lsl() function
|
| /external/v8/src/arm64/ |
| D | assembler-arm64.h | 1425 void lsl(const Register& rd, const Register& rn, int shift) { in lsl() function
|
| /external/vixl/benchmarks/aarch32/ |
| D | asm-disasm-speed-test.cc | 475 __ lsl(r2, r8, r5); in Generate_3() local
483 __ lsl(r8, r8, r0); in Generate_3() local
2842 __ lsl(r1, r8, lr); in Generate_22() local
2850 __ lsl(r8, r8, r0); in Generate_22() local
4894 __ lsl(r9, r3, 5U); in Generate_37() local
5422 __ lsl(r4, sl, 5U); in Generate_41() local
5502 __ lsl(sl, r6, 5U); in Generate_42() local
5538 __ lsl(lr, r4, 5U); in Generate_42() local
5562 __ lsl(r7, fp, 5U); in Generate_42() local
8905 __ lsl(r0, r2, r1); in Generate_67() local
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 228 __ lsl(w5, w6, 2); in GenerateTestSequenceBase() local
229 __ lsl(x7, x8, 3); in GenerateTestSequenceBase() local
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 2551 void lsl(Register rd, Register rm, const Operand& operand) { in lsl() function
2554 void lsl(Condition cond, Register rd, Register rm, const Operand& operand) { in lsl() function
2557 void lsl(EncodingSize size, in lsl() function
|
| D | assembler-aarch32.cc | 6708 void Assembler::lsl(Condition cond, in lsl() function in vixl::aarch32::Assembler
|
| D | disasm-aarch32.cc | 1842 void Disassembler::lsl(Condition cond, in lsl() function in vixl::aarch32::Disassembler
|
| /external/swiftshader/third_party/subzero/src/ |
| D | IceAssemblerARM32.cpp | 1735 void AssemblerARM32::lsl(const Operand *OpRd, const Operand *OpRm, in lsl() function in Ice::ARM32::AssemblerARM32
|
| /external/v8/src/arm/ |
| D | assembler-arm.cc | 1667 void Assembler::lsl(Register dst, Register src1, const Operand& src2, SBit s, in lsl() function in v8::internal::Assembler
|