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Searched refs:hasQPX (Results 1 – 12 of 12) sorted by relevance

/external/llvm/lib/Target/PowerPC/
DPPCTargetTransformInfo.cpp222 if (Vector && !ST->hasAltivec() && !ST->hasQPX()) in getNumberOfRegisters()
229 if (ST->hasQPX()) return 256; in getRegisterBitWidth()
326 } else if (ST->hasQPX() && Val->getScalarType()->isFloatingPointTy()) { in getVectorInstrCost()
372 bool IsQPXType = ST->hasQPX() && in getMemoryOpCost()
DPPCSubtarget.h240 bool hasQPX() const { return HasQPX; } in hasQPX() function
269 if ((hasQPX() || isBGQ()) && !isQPXStackUnaligned()) in getPlatformStackAlignment()
DPPCCallingConv.td64 CCIfSubtarget<"hasQPX()", CCAssignToReg<[QF1, QF2]>>>,
120 CCIfSubtarget<"hasQPX()", CCAssignToReg<[QF1, QF2]>>>,
186 CCIfType<[v4f64, v4f32, v4i1], CCIfSubtarget<"hasQPX()",
DPPCISelLowering.cpp674 if (Subtarget.hasQPX()) { in PPCTargetLowering()
997 if (Subtarget.hasAltivec() || Subtarget.hasQPX()) in getByValTypeAlignment()
998 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16); in getByValTypeAlignment()
1108 if (Subtarget.hasQPX()) in getSetCCResultType()
1998 if (!Subtarget.hasQPX() || (VT != MVT::v4f64 && VT != MVT::v4f32)) { in getPreIndexedAddressParts()
2968 RC = Subtarget.hasQPX() ? &PPC::QSRCRegClass : &PPC::VRRCRegClass; in LowerFormalArguments_32SVR4()
3184 Subtarget.hasQPX())) in LowerFormalArguments_64SVR4()
3433 if (!Subtarget.hasQPX()) { in LowerFormalArguments_64SVR4()
3997 Subtarget.hasQPX())) in needStackSlotPassParameters()
5084 if (Subtarget.hasQPX()) { in LowerCall_64SVR4()
[all …]
DPPCISelDAGToDAG.cpp2358 if (PPCSubTarget->hasQPX()) in trySETCC()
2840 else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4f64) in Select()
2842 else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4f32) in Select()
2844 else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4i1) in Select()
DPPCInstrQPX.td105 def HasQPX : Predicate<"PPCSubTarget->hasQPX()">;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCTargetTransformInfo.cpp260 if (Vector && !ST->hasAltivec() && !ST->hasQPX()) in getNumberOfRegisters()
267 if (ST->hasQPX()) return 256; in getRegisterBitWidth()
375 } else if (ST->hasQPX() && Val->getScalarType()->isFloatingPointTy()) { in getVectorInstrCost()
416 bool IsQPXType = ST->hasQPX() && in getMemoryOpCost()
DPPCSubtarget.h245 bool hasQPX() const { return HasQPX; } in hasQPX() function
275 if ((hasQPX() || isBGQ()) && !isQPXStackUnaligned()) in getPlatformStackAlignment()
DPPCCallingConv.td65 CCIfSubtarget<"hasQPX()", CCAssignToReg<[QF1]>>>,
102 CCIfSubtarget<"hasQPX()", CCAssignToReg<[QF1, QF2]>>>,
159 CCIfSubtarget<"hasQPX()", CCAssignToReg<[QF1, QF2]>>>,
239 CCIfType<[v4f64, v4f32, v4i1], CCIfSubtarget<"hasQPX()",
DPPCISelLowering.cpp877 if (Subtarget.hasQPX()) { in PPCTargetLowering()
1221 if (Subtarget.hasAltivec() || Subtarget.hasQPX()) in getByValTypeAlignment()
1222 getMaxByValAlign(Ty, Align, Subtarget.hasQPX() ? 32 : 16); in getByValTypeAlignment()
1367 if (Subtarget.hasQPX()) in getSetCCResultType()
2436 if (!Subtarget.hasQPX() || (VT != MVT::v4f64 && VT != MVT::v4f32)) { in getPreIndexedAddressParts()
3456 RC = Subtarget.hasQPX() ? &PPC::QSRCRegClass : &PPC::VRRCRegClass; in LowerFormalArguments_32SVR4()
3667 Subtarget.hasQPX())) in LowerFormalArguments_64SVR4()
3918 if (!Subtarget.hasQPX()) { in LowerFormalArguments_64SVR4()
4494 Subtarget.hasQPX())) in needStackSlotPassParameters()
5590 Subtarget.hasQPX())) in LowerCall_64SVR4()
[all …]
DPPCISelDAGToDAG.cpp3949 if (PPCSubTarget->hasQPX() || PPCSubTarget->hasSPE()) in trySETCC()
4634 else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4f64) in Select()
4636 else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4f32) in Select()
4638 else if (PPCSubTarget->hasQPX() && N->getValueType(0) == MVT::v4i1) in Select()
DPPCInstrQPX.td105 def HasQPX : Predicate<"PPCSubTarget->hasQPX()">;