Home
last modified time | relevance | path

Searched +full:- +full:4 (Results 1 – 25 of 1797) sorted by relevance

12345678910>>...72

/external/llvm-project/llvm/test/CodeGen/AArch64/
Dminmax-of-minmax.ll2 ; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s
4 ; There are 4 commuted variants (abbc/abcb/bcab/bcba) *
5 ; 4 predicate variants ([*][lg][te]) *
6 ; 4 min/max flavors (smin/smax/umin/umax) *
10 define <4 x i32> @smin_ab_bc(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
11 ; CHECK-LABEL: smin_ab_bc:
13 ; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
14 ; CHECK-NEXT: smin v1.4s, v1.4s, v2.4s
15 ; CHECK-NEXT: smin v0.4s, v0.4s, v1.4s
16 ; CHECK-NEXT: ret
[all …]
Dsrem-seteq-vec-nonsplat.ll2 ; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
5 define <4 x i32> @test_srem_odd_even(<4 x i32> %X) nounwind {
6 ; CHECK-LABEL: test_srem_odd_even:
8 ; CHECK-NEXT: adrp x8, .LCPI0_0
9 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI0_0]
10 ; CHECK-NEXT: adrp x8, .LCPI0_1
11 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI0_1]
12 ; CHECK-NEXT: adrp x8, .LCPI0_2
13 ; CHECK-NEXT: smull2 v3.2d, v0.4s, v1.4s
14 ; CHECK-NEXT: smull v1.2d, v0.2s, v1.2s
[all …]
Durem-seteq-vec-nonsplat.ll2 ; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
5 define <4 x i32> @test_urem_odd_even(<4 x i32> %X) nounwind {
6 ; CHECK-LABEL: test_urem_odd_even:
8 ; CHECK-NEXT: adrp x8, .LCPI0_0
9 ; CHECK-NEXT: ldr q1, [x8, :lo12:.LCPI0_0]
10 ; CHECK-NEXT: adrp x8, .LCPI0_1
11 ; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI0_1]
12 ; CHECK-NEXT: adrp x8, .LCPI0_2
13 ; CHECK-NEXT: ldr q3, [x8, :lo12:.LCPI0_2]
14 ; CHECK-NEXT: neg v1.4s, v1.4s
[all …]
Dfp16-v4-instructions.ll1 …RUN: llc < %s -asm-verbose=false -mtriple=aarch64-none-eabi -mattr=-fullfp16 | FileCheck %s --chec…
2 …RUN: llc < %s -asm-verbose=false -mtriple=aarch64-none-eabi -mattr=+fullfp16 | FileCheck %s --chec…
4 define <4 x half> @add_h(<4 x half> %a, <4 x half> %b) {
6 ; CHECK-CVT-LABEL: add_h:
7 ; CHECK-CVT-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
8 ; CHECK-CVT-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
9 ; CHECK-CVT-NEXT: fadd [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
10 ; CHECK-CVT-NEXT: fcvtn v0.4h, [[RES]]
12 ; CHECK-FP16-LABEL: add_h:
13 ; CHECK-FP16: fadd v0.4h, v0.4h, v1.4h
[all …]
Dsrem-seteq-vec-splat.ll2 ; RUN: llc -mtriple=aarch64-unknown-linux-gnu < %s | FileCheck %s
5 define <4 x i32> @test_srem_odd_25(<4 x i32> %X) nounwind {
6 ; CHECK-LABEL: test_srem_odd_25:
8 ; CHECK-NEXT: mov w8, #23593
9 ; CHECK-NEXT: mov w9, #47185
10 ; CHECK-NEXT: movk w8, #49807, lsl #16
11 ; CHECK-NEXT: movk w9, #1310, lsl #16
12 ; CHECK-NEXT: mov w10, #28834
13 ; CHECK-NEXT: movk w10, #2621, lsl #16
14 ; CHECK-NEXT: dup v1.4s, w8
[all …]
/external/autotest/client/profilers/oprofile/
Doprofile-0.9.4.tar.bz2
/external/bc/tests/bc/errors/
D02.txt1 obase^= 20-f-b-4^-f-4-4^-f-4^-d
2 -f-4>-f-4^-0;759634576394-f-4^-f-4-4^-f-4^-4
3 -f-4^-f>4^-4-f-f-4^-f-4-4^-f-4^-d
4 -f-4>-f-4^-0;7-f-4^-f-4-4^-f-4^-4
5 -f-4^-f>4^-4-f-b-4^-f-4-4^-f-4^-d
6 -f-4>-f-4^-0;7454-f-4^-f-4-4^-f-4^-4
7 -f-4^-f>4^-4-f-f-4^-f-4-4^-f-4^-d
8 -f-4>-f-4^-0;75576394.3946587934658364894^-4-f-f-4^-f-4-4-4^-f-4-4^-f-4^-4
9 -f*.^-f>4^-4-f-b-4^-f-4-4^-f-4^-d
10 -f-4>-f-4^-0;759634576394-f-4^-f-4-4^-f-4^-4
[all …]
/external/llvm/test/CodeGen/PowerPC/
Dp9-xxinsertw-xxextractuw.ll1 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \
2 ; RUN: -verify-machineinstrs < %s | FileCheck %s
3 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu \
4 ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-BE
6 define <4 x float> @_Z7testInsILj0ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
8 ; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_
11 ; CHECK-BE-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_
12 ; CHECK-BE: xxsldwi 0, 35, 35, 3
13 ; CHECK-BE: xxinsertw 34, 0, 0
14 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
[all …]
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dp9-xxinsertw-xxextractuw.ll1 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-linux-gnu \
2 ; RUN: -verify-machineinstrs < %s | FileCheck %s
3 ; RUN: llc -mcpu=pwr9 -mtriple=powerpc64-unknown-linux-gnu \
4 ; RUN: -verify-machineinstrs < %s | FileCheck %s --check-prefix=CHECK-BE
6 define <4 x float> @_Z7testInsILj0ELj0EDv4_fET1_S1_S1_(<4 x float> %a, <4 x float> %b) {
8 ; CHECK-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_
11 ; CHECK-BE-LABEL: _Z7testInsILj0ELj0EDv4_fET1_S1_S1_
12 ; CHECK-BE: xxsldwi 0, 35, 35, 3
13 ; CHECK-BE: xxinsertw 34, 0, 0
14 %vecins = shufflevector <4 x float> %a, <4 x float> %b, <4 x i32> <i32 4, i32 1, i32 2, i32 3>
[all …]
/external/google-breakpad/src/tools/windows/dump_syms/testdata/
Domap_reorder_bbs.sym5 FILE 4 f:\dd\public\sdk\inc\internal\ntconfig.h
292 2d3c 4 65 1
293 FUNC 4b70 a 0 static int google_breakpad::i()
294 4b70 3 51 1
295 4b73 5 52 1
296 4b78 2 53 1
323 FUNC 198c 4 0 static void fast_error_exit(int)
326 FUNC 4d0c 5 0 static void fast_error_exit(int)
329 4d0c 5 337 4250
354 39a2 4 263 4250
[all …]
/external/llvm-project/llvm/test/Transforms/GVN/
Dnon-integral-pointers.ll2 ; RUN: opt -gvn -S < %s | FileCheck %s
4 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128-ni:4:5"
5 target triple = "x86_64-unknown-linux-gnu"
8 ; CHECK-LABEL: @f0(
9 ; CHECK-NEXT: entry:
10 ; CHECK-NEXT: store i64 [[VAL:%.*]], i64* [[LOC:%.*]], align 8
11 ; CHECK-NEXT: br i1 [[ALWAYSFALSE:%.*]], label [[NEVERTAKEN:%.*]], label [[ALWAYSTAKEN:%.*]]
13 ; CHECK-NEXT: [[LOC_BC:%.*]] = bitcast i64* [[LOC]] to i8 addrspace(4)**
14 ; CHECK-NEXT: [[PTR:%.*]] = load i8 addrspace(4)*, i8 addrspace(4)** [[LOC_BC]], align 8
15 ; CHECK-NEXT: store i8 5, i8 addrspace(4)* [[PTR]], align 1
[all …]
/external/antlr/runtime/C/dist/
Dlibantlr3c-3.1.4-SNAPSHOT.tar.gz
/external/google-breakpad/src/processor/testdata/symbols/kernel32.pdb/BCE8785C57B44245A669896B6A19B9542/
Dkernel32.sym3 PUBLIC 9b47 4 CloseHandle
6 PUBLIC be41 4 BaseDllMapResourceIdA
8 PUBLIC 936b 4 BaseSetLastNTError
9 PUBLIC 92b0 4 SetLastError
15 PUBLIC 29f30 4 SetUpHandles
17 PUBLIC 12f39 4 GetStdHandle
18 PUBLIC 17889 4 BaseDllInitializeIniFileMappings
28 PUBLIC 992f 4 LocalFree
30 PUBLIC 32eb1 4 LocalUnlock
31 PUBLIC 32e1d 4 LocalLock
[all …]
/external/llvm-project/llvm/test/CodeGen/Thumb2/
Dmve-vpt-blocks.ll2 ; RUN: llc -O3 -mtriple=thumbv8.1m.main-none-none-eabi --verify-machineinstrs -mattr=+mve.fp %s -o …
4 declare <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>)
6 define arm_aapcs_vfpcc <4 x i32> @vpt_block(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
7 ; CHECK-LABEL: vpt_block:
9 ; CHECK-NEXT: vpt.s32 ge, q0, q2
10 ; CHECK-NEXT: vorrt q0, q1, q2
11 ; CHECK-NEXT: bx lr
13 %0 = icmp sge <4 x i32> %a, %c
14 …%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x …
15 ret <4 x i32> %1
[all …]
Dmve-gather-ind32-unscaled.ll2 ; RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp %s -o 2>/dev/null - | FileCheck %s
4 define arm_aapcs_vfpcc <4 x i32> @zext_unscaled_i8_i32(i8* %base, <4 x i32>* %offptr) {
5 ; CHECK-LABEL: zext_unscaled_i8_i32:
7 ; CHECK-NEXT: vldrw.u32 q1, [r1]
8 ; CHECK-NEXT: vldrb.u32 q0, [r0, q1]
9 ; CHECK-NEXT: bx lr
11 %offs = load <4 x i32>, <4 x i32>* %offptr, align 4
12 %ptrs = getelementptr inbounds i8, i8* %base, <4 x i32> %offs
13 …%gather = call <4 x i8> @llvm.masked.gather.v4i8.v4p0i8(<4 x i8*> %ptrs, i32 1, <4 x i1> <i1 true,…
14 %gather.zext = zext <4 x i8> %gather to <4 x i32>
[all …]
/external/llvm-project/llvm/test/Transforms/SLPVectorizer/X86/
Daddsub.ll2 ; RUN: opt < %s -basic-aa -slp-vectorizer -S | FileCheck %s
3 target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
4 target triple = "x86_64-unknown-linux-gnu"
6 @b = common global [4 x i32] zeroinitializer, align 16
7 @c = common global [4 x i32] zeroinitializer, align 16
8 @d = common global [4 x i32] zeroinitializer, align 16
9 @e = common global [4 x i32] zeroinitializer, align 16
10 @a = common global [4 x i32] zeroinitializer, align 16
11 @fb = common global [4 x float] zeroinitializer, align 16
12 @fc = common global [4 x float] zeroinitializer, align 16
[all …]
/external/deqp-deps/glslang/Test/baseResults/
Dglsl.450.subgroupPartitioned.comp.out18 0:17 4 (const uint)
20 0:19 move second child to first child ( temp 4-component vector of uint)
21 0:19 'ballot' ( temp 4-component vector of uint)
22 0:19 subgroupPartitionNV ( global 4-component vector of uint)
24 0:21 move second child to first child ( temp 4-component vector of uint)
25 0:21 u4: direct index for structure (layout( column_major shared) buffer 4-component vector …
26 …4-component vector of float f4, layout( column_major shared) buffer 4-component vector of int i4, …
27 …4-element array of block{layout( column_major shared) buffer 4-component vector of float f4, layou…
31 0:21 subgroupPartitionNV ( global 4-component vector of uint)
33 0:21 f4: direct index for structure (layout( column_major shared) buffer 4-component vec…
[all …]
Dglsl.450.subgroupQuad.comp.out18 0:17 4 (const uint)
21 0:19 f4: direct index for structure (layout( column_major shared) buffer 4-component vecto…
22 …4-component vector of float f4, layout( column_major shared) buffer 4-component vector of int i4, …
23 …4-element array of block{layout( column_major shared) buffer 4-component vector of float f4, layou…
31 0:19 f4: direct index for structure (layout( column_major shared) buffer 4-component vec…
32 …4-component vector of float f4, layout( column_major shared) buffer 4-component vector of int i4, …
33 …4-element array of block{layout( column_major shared) buffer 4-component vector of float f4, layou…
42 0:20 move second child to first child ( temp 2-component vector of float)
43 0:20 vector swizzle ( temp 2-component vector of float)
44 0:20 f4: direct index for structure (layout( column_major shared) buffer 4-component vecto…
[all …]
Dglsl.450.subgroupShuffleRelative.comp.out18 0:17 4 (const uint)
21 0:19 f4: direct index for structure (layout( column_major shared) buffer 4-component vecto…
22 …4-component vector of float f4, layout( column_major shared) buffer 4-component vector of int i4, …
23 …4-element array of block{layout( column_major shared) buffer 4-component vector of float f4, layou…
31 0:19 f4: direct index for structure (layout( column_major shared) buffer 4-component vec…
32 …4-component vector of float f4, layout( column_major shared) buffer 4-component vector of int i4, …
33 …4-element array of block{layout( column_major shared) buffer 4-component vector of float f4, layou…
41 0:20 move second child to first child ( temp 2-component vector of float)
42 0:20 vector swizzle ( temp 2-component vector of float)
43 0:20 f4: direct index for structure (layout( column_major shared) buffer 4-component vecto…
[all …]
Dglsl.450.subgroupShuffle.comp.out18 0:17 4 (const uint)
21 0:19 f4: direct index for structure (layout( column_major shared) buffer 4-component vecto…
22 …4-component vector of float f4, layout( column_major shared) buffer 4-component vector of int i4, …
23 …4-element array of block{layout( column_major shared) buffer 4-component vector of float f4, layou…
31 0:19 f4: direct index for structure (layout( column_major shared) buffer 4-component vec…
32 …4-component vector of float f4, layout( column_major shared) buffer 4-component vector of int i4, …
33 …4-element array of block{layout( column_major shared) buffer 4-component vector of float f4, layou…
41 0:20 move second child to first child ( temp 2-component vector of float)
42 0:20 vector swizzle ( temp 2-component vector of float)
43 0:20 f4: direct index for structure (layout( column_major shared) buffer 4-component vecto…
[all …]
/external/llvm/test/Transforms/InstCombine/
Dx86-vperm2.ll1 ; RUN: opt < %s -instcombine -S | FileCheck %s
3 ; This should never happen, but make sure we don't crash handling a non-constant immediate byte.
5 define <4 x double> @perm2pd_non_const_imm(<4 x double> %a0, <4 x double> %a1, i8 %b) {
6 …%res = call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1, i8 %b…
7 ret <4 x double> %res
9 ; CHECK-LABEL: @perm2pd_non_const_imm
10 ; CHECK-NEXT: call <4 x double> @llvm.x86.avx.vperm2f128.pd.256(<4 x double> %a0, <4 x double> %a1…
11 ; CHECK-NEXT: ret <4 x double>
15 ; In the following 4 tests, both zero mask bits of the immediate are set.
17 define <4 x double> @perm2pd_0x88(<4 x double> %a0, <4 x double> %a1) {
[all …]
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dshuffle_select.ll2 ; RUN: opt < %s -instcombine -S | FileCheck %s
5 ; PR37806 - https://bugs.llvm.org/show_bug.cgi?id=37806
7 define <4 x i32> @add(<4 x i32> %v) {
8 ; CHECK-LABEL: @add(
9 ; CHECK-NEXT: [[S:%.*]] = add <4 x i32> [[V:%.*]], <i32 11, i32 0, i32 13, i32 0>
10 ; CHECK-NEXT: ret <4 x i32> [[S]]
12 %b = add <4 x i32> %v, <i32 11, i32 12, i32 13, i32 14>
13 %s = shufflevector <4 x i32> %b, <4 x i32> %v, <4 x i32> <i32 0, i32 5, i32 2, i32 7>
14 ret <4 x i32> %s
19 define <4 x i32> @add_nuw_nsw(<4 x i32> %v) {
[all …]
Dvector-mul.ll2 ; RUN: opt < %s -instcombine -S | FileCheck %s
5 ; of known constant power-of-2 elements with vector shift.
7 define <4 x i8> @Zero_i8(<4 x i8> %InVec) {
8 ; CHECK-LABEL: @Zero_i8(
9 ; CHECK-NEXT: entry:
10 ; CHECK-NEXT: ret <4 x i8> zeroinitializer
13 %mul = mul <4 x i8> %InVec, <i8 0, i8 0, i8 0, i8 0>
14 ret <4 x i8> %mul
17 define <4 x i8> @Identity_i8(<4 x i8> %InVec) {
18 ; CHECK-LABEL: @Identity_i8(
[all …]
/external/llvm-project/llvm/test/MC/Mips/
Dmips64-instalias-imm-expanding.s1 # RUN: llvm-mc -triple mips64el-unknown-linux -show-encoding -print-imm-hex %s | FileCheck %s
6 add $4, -0x80000000
7 # CHECK-NEXT: lui $1, 0x8000 # encoding: [0x00,0x80,0x01,0x3c]
8 # CHECK-NEXT: add $4, $4, $1 # encoding: [0x20,0x20,0x81,0x00]
9 add $4, -0x8001
10 # CHECK-NEXT: lui $1, 0xffff # encoding: [0xff,0xff,0x01,0x3c]
11 # CHECK-NEXT: ori $1, $1, 0x7fff # encoding: [0xff,0x7f,0x21,0x34]
12 # CHECK-NEXT: add $4, $4, $1 # encoding: [0x20,0x20,0x81,0x00]
13 add $4, -0x8000
14 # CHECK-NEXT: addi $4, $4, -0x8000 # encoding: [0x00,0x80,0x84,0x20]
[all …]
/external/llvm-project/llvm/test/CodeGen/SystemZ/
Dvec-cmp-07.ll3 ; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
6 define <4 x i32> @f1(<4 x i32> %dummy, <4 x float> %val1, <4 x float> %val2) {
7 ; CHECK-LABEL: f1:
9 ; CHECK-NEXT: br %r14
10 %cmp = fcmp oeq <4 x float> %val1, %val2
11 %ret = sext <4 x i1> %cmp to <4 x i32>
12 ret <4 x i32> %ret
16 define <4 x i32> @f2(<4 x i32> %dummy, <4 x float> %val1, <4 x float> %val2) {
17 ; CHECK-LABEL: f2:
18 ; CHECK-DAG: vfchsb [[REG1:%v[0-9]+]], %v28, %v26
[all …]

12345678910>>...72