Home
last modified time | relevance | path

Searched +full:llvm +full:- +full:3 (Results 1 – 25 of 1355) sorted by relevance

12345678910>>...55

/external/llvm-project/llvm/test/Analysis/CostModel/X86/
Darith-fix.ll2 ; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mattr=+ssse3 | FileCheck %…
3 ; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mattr=+sse4.2 | FileCheck …
4 ; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mattr=+avx | FileCheck %s …
5 ; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mattr=+avx2 | FileCheck %s…
6 ; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mattr=+avx512f | FileCheck…
7 ; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mattr=+avx512f,+avx512bw |…
8 ; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mattr=+avx512f,+avx512dq |…
10 ; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mcpu=slm | FileCheck %s --…
11 ; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mcpu=goldmont | FileCheck …
12 ; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mcpu=btver2 | FileCheck %s…
[all …]
Dfshr.ll2 ; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mattr=+ssse3 | FileCheck %…
3 ; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mattr=+sse4.2 | FileCheck …
4 ; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mattr=+avx | FileCheck %s …
5 ; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mattr=+avx2 | FileCheck %s…
6 ; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mattr=+avx512f | FileCheck…
7 ; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mattr=+avx512f,+avx512bw |…
8 ; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mattr=+avx512f,+avx512dq |…
10 ; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mcpu=slm | FileCheck %s --…
11 ; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mcpu=goldmont | FileCheck …
12 ; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mcpu=bdver2 | FileCheck %s…
[all …]
Dfshl.ll2 ; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mattr=+ssse3 | FileCheck %…
3 ; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mattr=+sse4.2 | FileCheck …
4 ; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mattr=+avx | FileCheck %s …
5 ; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mattr=+avx2 | FileCheck %s…
6 ; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mattr=+avx512f | FileCheck…
7 ; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mattr=+avx512f,+avx512bw |…
8 ; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mattr=+avx512f,+avx512dq |…
10 ; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mcpu=slm | FileCheck %s --…
11 ; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mcpu=goldmont | FileCheck …
12 ; RUN: opt < %s -cost-model -analyze -mtriple=x86_64-apple-macosx10.8.0 -mcpu=bdver2 | FileCheck %s…
[all …]
/external/llvm-project/mlir/test/Conversion/VectorToLLVM/
Dvector-to-llvm.mlir1 // RUN: mlir-opt %s -convert-vector-to-llvm | FileCheck %s
3 func @broadcast_vec1d_from_scalar(%arg0: f32) -> vector<2xf32> {
7 // CHECK-LABEL: llvm.func @broadcast_vec1d_from_scalar(
8 // CHECK-SAME: %[[A:.*]]: !llvm.float)
9 // CHECK: %[[T0:.*]] = llvm.mlir.undef : !llvm.vec<2 x float>
10 // CHECK: %[[T1:.*]] = llvm.mlir.constant(0 : i32) : !llvm.i32
11 // CHECK: %[[T2:.*]] = llvm.insertelement %[[A]], %[[T0]][%[[T1]] : !llvm.i32] : !llvm.vec<2 …
12 // CHECK: %[[T3:.*]] = llvm.shufflevector %[[T2]], %[[T0]] [0 : i32, 0 : i32] : !llvm.vec<2 x…
13 // CHECK: llvm.return %[[T3]] : !llvm.vec<2 x float>
15 func @broadcast_vec2d_from_scalar(%arg0: f32) -> vector<2x3xf32> {
[all …]
/external/llvm-project/mlir/test/Conversion/GPUCommon/
Dmemory-attrbution.mlir1 // RUN: mlir-opt -allow-unregistered-dialect --convert-gpu-to-nvvm --split-input-file %s | FileChec…
2 // RUN: mlir-opt -allow-unregistered-dialect --convert-gpu-to-rocdl --split-input-file %s | FileChe…
5 // NVVM-LABEL: llvm.func @private
8 // NVVM: %[[size:.*]] = llvm.mlir.constant(4 : i64) : !llvm.i64
9 // NVVM: %[[raw:.*]] = llvm.alloca %[[size]] x !llvm.float : (!llvm.i64) -> !llvm.ptr<float>
11 // ROCDL: %[[size:.*]] = llvm.mlir.constant(4 : i64) : !llvm.i64
12 // ROCDL: %[[raw:.*]] = llvm.alloca %[[size]] x !llvm.float : (!llvm.i64) -> !llvm.ptr<float, 5>
15 …// NVVM: %[[descr1:.*]] = llvm.mlir.undef : !llvm.struct<(ptr<float>, ptr<float>, i64, array<1 x i…
16 // NVVM: %[[descr2:.*]] = llvm.insertvalue %[[raw]], %[[descr1]][0]
17 // NVVM: %[[descr3:.*]] = llvm.insertvalue %[[raw]], %[[descr2]][1]
[all …]
/external/llvm-project/llvm/test/Analysis/CostModel/AMDGPU/
Dfma.ll1 ; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx900 -mattr=+half-rate-64-o…
2 ; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa -mattr=-half-rate-64-ops < %s | File…
3 …RUN: opt -cost-model -cost-kind=code-size -analyze -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx900 -ma…
4 ; RUN: opt -cost-model -cost-kind=code-size -analyze -mtriple=amdgcn-unknown-amdhsa -mattr=-half-ra…
6 ; ALL-LABEL: 'fma_f32'
7 ; SLOWF32: estimated cost of 4 for {{.*}} call float @llvm.fma.f32
8 ; FASTF32: estimated cost of 2 for {{.*}} call float @llvm.fma.f32
9 ; SIZEALL: estimated cost of 2 for {{.*}} call float @llvm.fma.f32
12 %fma = call float @llvm.fma.f32(float %vec, float %vec, float %vec) #1
17 ; ALL-LABEL: 'fma_v2f32'
[all …]
Dfabs.ll1 ; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck %s
2 ; RUN: opt -cost-model -cost-kind=code-size -analyze -mtriple=amdgcn-unknown-amdhsa < %s | FileChec…
4 ; CHECK-LABEL: 'fabs_f32'
5 ; CHECK: estimated cost of 0 for {{.*}} call float @llvm.fabs.f32
8 %fabs = call float @llvm.fabs.f32(float %vec) #1
13 ; CHECK-LABEL: 'fabs_v2f32'
14 ; CHECK: estimated cost of 0 for {{.*}} call <2 x float> @llvm.fabs.v2f32
17 %fabs = call <2 x float> @llvm.fabs.v2f32(<2 x float> %vec) #1
22 ; CHECK-LABEL: 'fabs_v3f32'
23 ; CHECK: estimated cost of 0 for {{.*}} call <3 x float> @llvm.fabs.v3f32
[all …]
/external/llvm-project/mlir/test/Conversion/StandardToLLVM/
Dstandard-to-llvm.mlir1 // RUN: mlir-opt -allow-unregistered-dialect %s -convert-std-to-llvm -split-input-file -verify-diag…
3 // CHECK-LABEL: func @address_space(
4 // CHECK-SAME: !llvm.ptr<float, 7>
5 func @address_space(%arg0 : memref<32xf32, affine_map<(d0) -> (d0)>, 7>) {
6 %0 = alloc() : memref<32xf32, affine_map<(d0) -> (d0)>, 5>
8 // CHECK: llvm.load %{{.*}} : !llvm.ptr<float, 5>
9 %2 = load %0[%1] : memref<32xf32, affine_map<(d0) -> (d0)>, 5>
13 // -----
15 // CHECK-LABEL: func @rsqrt(
16 // CHECK-SAME: !llvm.float
[all …]
/external/llvm-project/mlir/test/Conversion/SPIRVToLLVM/
Dglsl-ops-to-llvm.mlir1 // RUN: mlir-opt -convert-spirv-to-llvm %s | FileCheck %s
3 //===----------------------------------------------------------------------===//
5 //===----------------------------------------------------------------------===//
7 // CHECK-LABEL: @ceil
8 spv.func @ceil(%arg0: f32, %arg1: vector<3xf16>) "None" {
9 // CHECK: "llvm.intr.ceil"(%{{.*}}) : (!llvm.float) -> !llvm.float
11 // CHECK: "llvm.intr.ceil"(%{{.*}}) : (!llvm.vec<3 x half>) -> !llvm.vec<3 x half>
12 %1 = spv.GLSL.Ceil %arg1 : vector<3xf16>
16 //===----------------------------------------------------------------------===//
18 //===----------------------------------------------------------------------===//
[all …]
Dcast-ops-to-llvm.mlir1 // RUN: mlir-opt -convert-spirv-to-llvm %s | FileCheck %s
3 //===----------------------------------------------------------------------===//
5 //===----------------------------------------------------------------------===//
7 // CHECK-LABEL: @bitcast_float_to_integer_scalar
9 // CHECK: llvm.bitcast {{.*}} : !llvm.float to !llvm.i32
14 // CHECK-LABEL: @bitcast_float_to_integer_vector
15 spv.func @bitcast_float_to_integer_vector(%arg0 : vector<3xf32>) "None" {
16 // CHECK: {{.*}} = llvm.bitcast {{.*}} : !llvm.vec<3 x float> to !llvm.vec<3 x i32>
17 %0 = spv.Bitcast %arg0: vector<3xf32> to vector<3xi32>
21 // CHECK-LABEL: @bitcast_vector_to_scalar
[all …]
/external/llvm-project/mlir/test/Dialect/Linalg/
Dllvm.mlir1 // RUN: mlir-opt %s -convert-linalg-to-llvm | FileCheck %s
9 // CHECK-LABEL: func @range(%{{.*}}: !llvm.i64) {
10 // CHECK: llvm.mlir.constant(0 : index) : !llvm.i64
11 // CHECK-NEXT: llvm.mlir.constant(1 : index) : !llvm.i64
12 // CHECK-NEXT: llvm.mlir.undef : !llvm.struct<(i64, i64, i64)>
13 // CHECK-NEXT: llvm.insertvalue %{{.*}}, %{{.*}}[0] : !llvm.struct<(i64, i64, i64)>
14 // CHECK-NEXT: llvm.insertvalue %{{.*}}, %{{.*}}[1] : !llvm.struct<(i64, i64, i64)>
15 // CHECK-NEXT: llvm.insertvalue %{{.*}}, %{{.*}}[2] : !llvm.struct<(i64, i64, i64)>
21 // CHECK-LABEL: func @slice
23 // CHECK: llvm.extractvalue %{{.*}}[4, 0] : !llvm.struct<(ptr<float>, ptr<float>, i64, arra…
[all …]
/external/llvm-project/clang/docs/
DClangFormattedStatus.rst4 .none { background-color: #FFCC99 }
5 .part { background-color: #FFFF99 }
6 .good { background-color: #2CCCFF }
7 .total { font-weight: bold; }
19 :doc:`ClangFormattedStatus` describes the state of LLVM source
20 …t` as of: December 04, 2020 17:56:14 (`840e651dc6d <https://github.com/llvm/llvm-project/commit/84…
23 .. list-table:: LLVM Clang-Format Status
25 :header-rows: 1
27 * - Directory
28 - Total Files
[all …]
/external/llvm-project/llvm/test/Transforms/InstCombine/
Dcopysign.ll2 ; RUN: opt -S -instcombine < %s | FileCheck %s
4 declare float @llvm.fabs.f32(float)
5 declare float @llvm.copysign.f32(float, float)
6 declare float @llvm.maxnum.f32(float, float)
7 declare <3 x double> @llvm.copysign.v3f64(<3 x double>, <3 x double>)
10 ; CHECK-LABEL: @positive_sign_arg(
11 ; CHECK-NEXT: [[TMP1:%.*]] = call arcp float @llvm.fabs.f32(float [[X:%.*]])
12 ; CHECK-NEXT: ret float [[TMP1]]
14 %r = call arcp float @llvm.copysign.f32(float %x, float 0.0)
18 define <3 x double> @positive_sign_arg_vec_splat(<3 x double> %x) {
[all …]
Dcommutative-intrinsics.ll2 ; RUN: opt -S -instcombine < %s | FileCheck %s
5 ; CHECK-LABEL: @smax(
6 ; CHECK-NEXT: [[R:%.*]] = call i35 @llvm.smax.i35(i35 [[X:%.*]], i35 42)
7 ; CHECK-NEXT: ret i35 [[R]]
9 %r = call i35 @llvm.smax.i35(i35 42, i35 %x)
14 ; CHECK-LABEL: @smin(
15 ; CHECK-NEXT: [[R:%.*]] = call i5 @llvm.smin.i5(i5 [[X:%.*]], i5 10)
16 ; CHECK-NEXT: ret i5 [[R]]
18 %r = call i5 @llvm.smin.i5(i5 42, i5 %x)
23 ; CHECK-LABEL: @umax(
[all …]
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dlds-alignment.ll1 ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa --amdhsa-code-object-version=2 < %s | FileC…
3 @lds.align16.0 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 16
4 @lds.align16.1 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 16
6 @lds.align8.0 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 8
7 @lds.align32.0 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 32
9 @lds.missing.align.0 = internal unnamed_addr addrspace(3) global [39 x i32] undef
10 @lds.missing.align.1 = internal unnamed_addr addrspace(3) global [7 x i64] undef
12 declare void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* nocapture, i8 addrspace(1)* nocapture read…
13 declare void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* nocapture, i8 addrspace(3)* nocapture read…
16 ; HSA-LABEL: {{^}}test_no_round_size_1:
[all …]
Dllvm.amdgcn.buffer.atomic.ll1 …RUN: llc < %s -march=amdgcn -mcpu=verde -amdgpu-atomic-optimizations=false -verify-machineinstrs |…
2 …RUN: llc < %s -march=amdgcn -mcpu=tonga -amdgpu-atomic-optimizations=false -verify-machineinstrs |…
4 ;CHECK-LABEL: {{^}}test1:
5 ;CHECK-NOT: s_waitcnt
6 ;CHECK: buffer_atomic_swap v0, off, s[0:3], 0 glc
7 ;VI: s_movk_i32 [[SOFS:s[0-9]+]], 0x1ffc
9 ;CHECK: buffer_atomic_swap v0, v1, s[0:3], 0 idxen glc
11 ;CHECK: buffer_atomic_swap v0, v2, s[0:3], 0 offen glc
13 ;CHECK: buffer_atomic_swap v0, v[1:2], s[0:3], 0 idxen offen glc
16 ;CHECK: buffer_atomic_swap v0, v2, s[0:3], 0 offen offset:42 glc
[all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/include/llvm/IR/
DIntrinsicsAMDGPU.h1 /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\
7 \*===----------------------------------------------------------------------===*/
12 namespace llvm {
16 amdgcn_alignbit = 821, // llvm.amdgcn.alignbit
17 amdgcn_alignbyte, // llvm.amdgcn.alignbyte
18 amdgcn_atomic_dec, // llvm.amdgcn.atomic.dec
19 amdgcn_atomic_inc, // llvm.amdgcn.atomic.inc
20 amdgcn_buffer_atomic_add, // llvm.amdgcn.buffer.atomic.add
21 amdgcn_buffer_atomic_and, // llvm.amdgcn.buffer.atomic.and
22 amdgcn_buffer_atomic_cmpswap, // llvm.amdgcn.buffer.atomic.cmpswap
[all …]
/external/llvm-project/clang/test/CodeGen/
Darm-v8.1a-neon-intrinsics.c1 // RUN: %clang_cc1 -triple armv8.1a-linux-gnu -target-abi apcs-gnu -target-feature +neon \
2 // RUN: -S -emit-llvm -o - %s \
3 // RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM
5 // RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \
6 // RUN: -target-feature +v8.1a -S -emit-llvm -o - %s \
7 // RUN: | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
9 // REQUIRES: arm-registered-target,aarch64-registered-target
13 // CHECK-LABEL: test_vqrdmlah_s16
15 // CHECK-ARM: call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}}) in test_vqrdmlah_s16()
16 // CHECK-ARM: call <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16> {{%.*}}, <4 x i16> {{%.*}}) in test_vqrdmlah_s16()
[all …]
/external/llvm-project/llvm/test/tools/llvm-readobj/ELF/
Dprogram-headers.test2 ## mapping (llvm-readelf only) with -l, --program-headers and --segments options.
4 ## Check that -l, --program-headers and --segments are the same option.
6 ## Case A: test llvm-readelf tool.
7 # RUN: yaml2obj --docnum=1 -DBITS=32 -DMACHINE=EM_386 %s -o %t32.elf
8 # RUN: llvm-readelf -l %t32.elf 2>&1 > %t.readelf-l.txt
9 # RUN: llvm-readelf --program-headers %t32.elf 2>&1 > %t.readelf-pheaders.txt
10 # RUN: cmp %t.readelf-l.txt %t.readelf-pheaders.txt
11 # RUN: llvm-readelf --segments %t32.elf 2>&1 > %t.readelf-segments.txt
12 # RUN: cmp %t.readelf-l.txt %t.readelf-segments.txt
14 ## Case B: test llvm-readobj tool.
[all …]
/external/llvm/test/CodeGen/AMDGPU/
Dlds-alignment.ll1 ; RUN: llc -march=amdgcn -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck -check-prefix=HSA -check-p…
3 @lds.align16.0 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 16
4 @lds.align16.1 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 16
6 @lds.align8.0 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 8
7 @lds.align32.0 = internal unnamed_addr addrspace(3) global [38 x i8] undef, align 32
9 @lds.missing.align.0 = internal unnamed_addr addrspace(3) global [39 x i32] undef
10 @lds.missing.align.1 = internal unnamed_addr addrspace(3) global [7 x i64] undef
12 declare void @llvm.memcpy.p3i8.p1i8.i32(i8 addrspace(3)* nocapture, i8 addrspace(1)* nocapture read…
13 declare void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* nocapture, i8 addrspace(3)* nocapture read…
16 ; HSA-LABEL: {{^}}test_no_round_size_1:
[all …]
/external/llvm-project/clang/test/CodeGen/X86/
D3dnow-builtins.c1 …_cc1 -ffreestanding %s -triple=x86_64-unknown-unknown -target-feature +3dnowa -emit-llvm -o - -Wal…
2 …ang_cc1 -ffreestanding %s -triple=x86_64-scei-ps4 -target-feature +3dnowa -emit-llvm -o - -Wall -W…
8 // PS4-LABEL: define i64 @test_m_pavgusb in test_m_pavgusb()
9 // GCC-LABEL: define double @test_m_pavgusb in test_m_pavgusb()
10 // CHECK: @llvm.x86.3dnow.pavgusb in test_m_pavgusb()
15 // PS4-LABEL: define i64 @test_m_pf2id in test_m_pf2id()
16 // GCC-LABEL: define double @test_m_pf2id in test_m_pf2id()
17 // CHECK: @llvm.x86.3dnow.pf2id in test_m_pf2id()
22 // PS4-LABEL: define i64 @test_m_pfacc in test_m_pfacc()
23 // GCC-LABEL: define double @test_m_pfacc in test_m_pfacc()
[all …]
/external/clang/test/CodeGen/
D3dnow-builtins.c1 …N: %clang_cc1 %s -triple=x86_64-unknown-unknown -target-feature +3dnowa -emit-llvm -o - -Werror | …
2 … RUN: %clang_cc1 %s -triple=x86_64-scei-ps4 -target-feature +3dnowa -emit-llvm -o - -Werror | File…
10 // PS4-LABEL: define i64 @test_m_pavgusb in test_m_pavgusb()
11 // GCC-LABEL: define double @test_m_pavgusb in test_m_pavgusb()
12 // CHECK: @llvm.x86.3dnow.pavgusb in test_m_pavgusb()
17 // PS4-LABEL: define i64 @test_m_pf2id in test_m_pf2id()
18 // GCC-LABEL: define double @test_m_pf2id in test_m_pf2id()
19 // CHECK: @llvm.x86.3dnow.pf2id in test_m_pf2id()
24 // PS4-LABEL: define i64 @test_m_pfacc in test_m_pfacc()
25 // GCC-LABEL: define double @test_m_pfacc in test_m_pfacc()
[all …]
/external/llvm-project/llvm/test/tools/llvm-objdump/ELF/PowerPC/
Ddebug-vars.s1 ## Check that the --debug-vars option works for simple register locations, when
5 ## clang --target=arm--none-eabi -march=armv7-a -c debug.c -O1 -gdwarf-3 -S -o -
7 ## clang --target=powerpc64-unknown-linux -c debug.c -O1 -S -o -
20 # RUN: llvm-mc -triple powerpc64-unknown-linux < %s -filetype=obj | \
21 # RUN: llvm-objdump - -d --debug-vars --no-show-raw-insn | \
25 # CHECK-EMPTY:
26 # CHECK-NEXT: 0000000000000000 <.text>:
27 # CHECK-NEXT: ┠─ a = S3
28 # CHECK-NEXT: ┃ ┠─ b = S4
29 # CHECK-NEXT: ┃ ┃ ┠─ c = S5
[all …]
/external/llvm-project/mlir/test/SDBM/
Dsdbm-api-test.cpp1 //===- sdbm-api-test.cpp - Tests for SDBM expression APIs -----------------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
9 // RUN: mlir-sdbm-api-test | FileCheck %s
16 #include "llvm/Support/raw_ostream.h"
34 d = ctx()->getOrLoadDialect<SDBMDialect>(); in dialect()
51 // d0 - 3 <= 0 <=> d0 <= 3. in TEST_FUNC()
52 auto sdbm = SDBM::get(dim(0) - 3, llvm::None); in TEST_FUNC()
[all …]
/external/llvm-project/llvm/test/CodeGen/X86/
Dmmx-intrinsics.ll1 ; RUN: llc < %s -mtriple=i686-- -mattr=+mmx,+ssse3,-avx | FileCheck %s --check-prefix=ALL --check-p…
2 ; RUN: llc < %s -mtriple=i686-- -mattr=+mmx,+avx | FileCheck %s --check-prefix=ALL --check-prefix=X…
3 ; RUN: llc < %s -mtriple=x86_64-- -mattr=+mmx,+ssse3,-avx | FileCheck %s --check-prefix=ALL --check…
4 ; RUN: llc < %s -mtriple=x86_64-- -mattr=+mmx,+avx | FileCheck %s --check-prefix=ALL --check-prefix…
6 declare x86_mmx @llvm.x86.ssse3.phadd.w(x86_mmx, x86_mmx) nounwind readnone
9 ; ALL-LABEL: @test1
15 %3 = bitcast <4 x i16> %0 to x86_mmx
16 %4 = tail call x86_mmx @llvm.x86.ssse3.phadd.w(x86_mmx %2, x86_mmx %3) nounwind readnone
23 declare x86_mmx @llvm.x86.mmx.pcmpgt.d(x86_mmx, x86_mmx) nounwind readnone
26 ; ALL-LABEL: @test88
[all …]

12345678910>>...55