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Searched refs:BaseOpcode (Results 1 – 25 of 93) sorted by relevance

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/external/llvm-project/llvm/lib/Target/X86/
DX86InstrFMA3Info.cpp132 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); in getFMA3Group() local
137 ((BaseOpcode >= 0x96 && BaseOpcode <= 0x9F) || in getFMA3Group()
138 (BaseOpcode >= 0xA6 && BaseOpcode <= 0xAF) || in getFMA3Group()
139 (BaseOpcode >= 0xB6 && BaseOpcode <= 0xBF)); in getFMA3Group()
156 unsigned FormIndex = ((BaseOpcode - 0x90) >> 4) & 0x3; in getFMA3Group()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrFMA3Info.cpp135 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); in getFMA3Group() local
140 ((BaseOpcode >= 0x96 && BaseOpcode <= 0x9F) || in getFMA3Group()
141 (BaseOpcode >= 0xA6 && BaseOpcode <= 0xAF) || in getFMA3Group()
142 (BaseOpcode >= 0xB6 && BaseOpcode <= 0xBF)); in getFMA3Group()
159 unsigned FormIndex = ((BaseOpcode - 0x90) >> 4) & 0x3; in getFMA3Group()
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DMIMGInstructions.td30 MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(NAME);
50 let Fields = ["BaseOpcode", "Store", "Atomic", "AtomicX2", "Sampler", "Gather4",
55 let PrimaryKey = ["BaseOpcode"];
145 MIMGBaseOpcode BaseOpcode;
154 let Fields = ["Opcode", "BaseOpcode", "MIMGEncoding", "VDataDwords", "VAddrDwords"];
158 let PrimaryKey = ["BaseOpcode", "MIMGEncoding", "VDataDwords", "VAddrDwords"];
190 let d16 = !if(BaseOpcode.HasD16, ?, 0);
201 let d16 = !if(BaseOpcode.HasD16, ?, 0);
218 let d16 = !if(BaseOpcode.HasD16, ?, 0);
230 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
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/external/llvm/lib/Target/Hexagon/
DHexagon.td82 // Instructions with the same BaseOpcode and isNVStore values form a row.
83 let RowFields = ["BaseOpcode", "isNVStore", "PNewValue", "isNT"];
98 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
110 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
122 let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
134 let RowFields = ["BaseOpcode", "PredSense", "isNVStore"];
146 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
158 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
224 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
232 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMicroMipsInstrFPU.td260 let BaseOpcode = "RECIP_D32";
272 let BaseOpcode = "RSQRT_D32";
283 let BaseOpcode = "LDC132";
297 let BaseOpcode = "c.f."#NAME;
302 let BaseOpcode = "c.un."#NAME;
307 let BaseOpcode = "c.eq."#NAME;
312 let BaseOpcode = "c.ueq."#NAME;
317 let BaseOpcode = "c.olt."#NAME;
321 let BaseOpcode = "c.ult."#NAME;
325 let BaseOpcode = "c.ole."#NAME;
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DMipsEVAInstrInfo.td61 string BaseOpcode = instr_asm;
80 string BaseOpcode = instr_asm;
97 string BaseOpcode = instr_asm;
115 string BaseOpcode = instr_asm;
131 string BaseOpcode = instr_asm;
145 string BaseOpcode = instr_asm;
171 string BaseOpcode = instr_asm;
DMipsInstrFPU.td285 let BaseOpcode = "c.f."#NAME;
290 let BaseOpcode = "c.un."#NAME;
295 let BaseOpcode = "c.eq."#NAME;
300 let BaseOpcode = "c.ueq."#NAME;
305 let BaseOpcode = "c.olt."#NAME;
309 let BaseOpcode = "c.ult."#NAME;
313 let BaseOpcode = "c.ole."#NAME;
317 let BaseOpcode = "c.ule."#NAME;
321 let BaseOpcode = "c.sf."#NAME;
326 let BaseOpcode = "c.ngle."#NAME;
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DMipsDSPInstrInfo.td274 string BaseOpcode = instr_asm;
285 string BaseOpcode = instr_asm;
296 string BaseOpcode = instr_asm;
307 string BaseOpcode = instr_asm;
319 string BaseOpcode = instr_asm;
330 string BaseOpcode = instr_asm;
341 string BaseOpcode = instr_asm;
351 string BaseOpcode = instr_asm;
363 string BaseOpcode = instr_asm;
374 string BaseOpcode = instr_asm;
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/external/llvm-project/llvm/lib/Target/Mips/
DMicroMipsInstrFPU.td260 let BaseOpcode = "RECIP_D32";
272 let BaseOpcode = "RSQRT_D32";
283 let BaseOpcode = "LDC132";
297 let BaseOpcode = "c.f."#NAME;
302 let BaseOpcode = "c.un."#NAME;
307 let BaseOpcode = "c.eq."#NAME;
312 let BaseOpcode = "c.ueq."#NAME;
317 let BaseOpcode = "c.olt."#NAME;
321 let BaseOpcode = "c.ult."#NAME;
325 let BaseOpcode = "c.ole."#NAME;
[all …]
DMipsEVAInstrInfo.td61 string BaseOpcode = instr_asm;
80 string BaseOpcode = instr_asm;
97 string BaseOpcode = instr_asm;
115 string BaseOpcode = instr_asm;
131 string BaseOpcode = instr_asm;
145 string BaseOpcode = instr_asm;
171 string BaseOpcode = instr_asm;
DMipsDSPInstrInfo.td274 string BaseOpcode = instr_asm;
285 string BaseOpcode = instr_asm;
296 string BaseOpcode = instr_asm;
307 string BaseOpcode = instr_asm;
319 string BaseOpcode = instr_asm;
330 string BaseOpcode = instr_asm;
341 string BaseOpcode = instr_asm;
351 string BaseOpcode = instr_asm;
363 string BaseOpcode = instr_asm;
374 string BaseOpcode = instr_asm;
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DMipsInstrFPU.td288 let BaseOpcode = "c.f."#NAME;
293 let BaseOpcode = "c.un."#NAME;
298 let BaseOpcode = "c.eq."#NAME;
303 let BaseOpcode = "c.ueq."#NAME;
308 let BaseOpcode = "c.olt."#NAME;
312 let BaseOpcode = "c.ult."#NAME;
316 let BaseOpcode = "c.ole."#NAME;
320 let BaseOpcode = "c.ule."#NAME;
324 let BaseOpcode = "c.sf."#NAME;
329 let BaseOpcode = "c.ngle."#NAME;
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/external/llvm-project/llvm/lib/Target/AMDGPU/
DMIMGInstructions.td30 MIMGBaseOpcode BaseOpcode = !cast<MIMGBaseOpcode>(NAME);
51 let Fields = ["BaseOpcode", "Store", "Atomic", "AtomicX2", "Sampler",
56 let PrimaryKey = ["BaseOpcode"];
161 MIMGBaseOpcode BaseOpcode;
170 let Fields = ["Opcode", "BaseOpcode", "MIMGEncoding", "VDataDwords", "VAddrDwords"];
174 let PrimaryKey = ["BaseOpcode", "MIMGEncoding", "VDataDwords", "VAddrDwords"];
206 let d16 = !if(BaseOpcode.HasD16, ?, 0);
217 let d16 = !if(BaseOpcode.HasD16, ?, 0);
234 let d16 = !if(BaseOpcode.HasD16, ?, 0);
246 !if(BaseOpcode.HasD16, (ins D16:$d16), (ins)));
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DAMDGPUInstrInfo.h53 unsigned BaseOpcode; member
80 const ImageDimIntrinsicInfo *getImageDimInstrinsicByBaseOpcode(unsigned BaseOpcode,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagon.td128 // Instructions with the same BaseOpcode and isNVStore values form a row.
129 let RowFields = ["BaseOpcode", "isNVStore", "PNewValue", "isBrTaken", "isNT"];
144 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
156 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
168 let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
180 let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
192 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
204 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
286 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
294 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
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DHexagonDepInstrInfo.td55 let BaseOpcode = "A2_add";
219 let BaseOpcode = "A2_addi";
305 let BaseOpcode = "A2_and";
344 let BaseOpcode = "A2_aslh";
356 let BaseOpcode = "A2_asrh";
431 let BaseOpcode = "A2_combinew";
590 let BaseOpcode = "A2_or";
634 let BaseOpcode = "A2_add";
651 let BaseOpcode = "A2_add";
666 let BaseOpcode = "A2_addi";
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/external/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp1424 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); in encodeInstruction() local
1427 BaseOpcode = 0x0F; // Weird 3DNow! encoding. in encodeInstruction()
1442 emitByte(BaseOpcode, OS); in encodeInstruction()
1451 emitByte(BaseOpcode + OpcodeOffset, OS); in encodeInstruction()
1463 emitByte(BaseOpcode, OS); in encodeInstruction()
1470 emitByte(BaseOpcode, OS); in encodeInstruction()
1478 emitByte(BaseOpcode, OS); in encodeInstruction()
1487 emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++)), OS); in encodeInstruction()
1491 emitByte(BaseOpcode, OS); in encodeInstruction()
1507 emitByte(BaseOpcode, OS); in encodeInstruction()
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/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagon.td157 // Instructions with the same BaseOpcode and isNVStore values form a row.
158 let RowFields = ["BaseOpcode", "isNVStore", "PNewValue", "isBrTaken", "isNT"];
173 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
185 let RowFields = ["BaseOpcode", "PNewValue", "isNVStore", "isBrTaken", "isNT"];
197 let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
209 let RowFields = ["BaseOpcode", "PredSense", "isNVStore", "isBrTaken"];
221 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
233 let RowFields = ["BaseOpcode", "PredSense", "PNewValue", "addrMode", "isNT"];
315 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
323 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
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DHexagonDepInstrInfo.td53 let BaseOpcode = "A2_add";
217 let BaseOpcode = "A2_addi";
303 let BaseOpcode = "A2_and";
344 let BaseOpcode = "A2_aslh";
356 let BaseOpcode = "A2_asrh";
430 let BaseOpcode = "A2_combinew";
588 let BaseOpcode = "A2_or";
632 let BaseOpcode = "A2_add";
649 let BaseOpcode = "A2_add";
664 let BaseOpcode = "A2_addi";
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp1408 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); in encodeInstruction() local
1411 BaseOpcode = 0x0F; // Weird 3DNow! encoding. in encodeInstruction()
1425 emitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1434 emitByte(BaseOpcode + OpcodeOffset, CurByte, OS); in encodeInstruction()
1446 emitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1453 emitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1461 emitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1470 emitByte(BaseOpcode + getX86RegNum(MI.getOperand(CurOp++)), CurByte, OS); in encodeInstruction()
1474 emitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1489 emitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
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/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp1191 uint8_t BaseOpcode = X86II::getBaseOpcodeFor(TSFlags); in encodeInstruction() local
1194 BaseOpcode = 0x0F; // Weird 3DNow! encoding. in encodeInstruction()
1216 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1229 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1239 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1243 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1248 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1255 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1263 EmitByte(BaseOpcode, CurByte, OS); in encodeInstruction()
1272 EmitByte(BaseOpcode + GetX86RegNum(MI.getOperand(CurOp++)), CurByte, OS); in encodeInstruction()
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/external/llvm/lib/Target/Mips/
DMicroMips64r6InstrInfo.td105 string BaseOpcode = instr_asm;
139 string BaseOpcode = "dclo";
149 string BaseOpcode = "dclz";
183 string BaseOpcode = instr_asm;
218 string BaseOpcode = instr_asm;
235 string BaseOpcode = instr_asm;
247 string BaseOpcode = instr_asm;
278 string BaseOpcode = instr_asm;
295 string BaseOpcode = "lld";
307 string BaseOpcode = "sd";
DMipsDSPInstrInfo.td267 string BaseOpcode = instr_asm;
278 string BaseOpcode = instr_asm;
289 string BaseOpcode = instr_asm;
300 string BaseOpcode = instr_asm;
312 string BaseOpcode = instr_asm;
323 string BaseOpcode = instr_asm;
334 string BaseOpcode = instr_asm;
344 string BaseOpcode = instr_asm;
356 string BaseOpcode = instr_asm;
367 string BaseOpcode = instr_asm;
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/external/llvm-project/llvm/docs/
DHowToUseInstrMappings.rst84 // instructions need to have same value for BaseOpcode field. It can be any
87 let RowFields = ["BaseOpcode"];
146 let BaseOpcode = "ADD";
154 let BaseOpcode = "ADD";
162 let BaseOpcode = "ADD";
169 ``PredRel`` is excluded from the analysis. ``BaseOpcode`` is another important
/external/llvm/docs/
DHowToUseInstrMappings.rst84 // instructions need to have same value for BaseOpcode field. It can be any
87 let RowFields = ["BaseOpcode"];
146 let BaseOpcode = "ADD";
154 let BaseOpcode = "ADD";
162 let BaseOpcode = "ADD";
169 ``PredRel`` is excluded from the analysis. ``BaseOpcode`` is another important

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