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Searched refs:CONV (Results 1 – 25 of 119) sorted by relevance

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/external/llvm-project/llvm/test/DebugInfo/X86/
D	convert-debugloc.ll	6 ; RUN: \| FileCheck %s --check-prefix=CONV "--implicit-check-not={{DW_TAG\|NULL}}" 12 ; RUN: \| FileCheck %s --check-prefix=CONV "--implicit-check-not={{DW_TAG\|NULL}}" 20 ; RUN: \| FileCheck %s --check-prefix=CONV "--implicit-check-not={{DW_TAG\|NULL}}" 24 ; RUN: \| FileCheck %s --check-prefix=CONV --check-prefix=SPLITCONV --check-prefix=SPLIT "--implic… 27 ; RUN: \| FileCheck %s --check-prefix=VERBOSE --check-prefix=CONV "--implicit-check-not={{DW_TAG\|N… 33 ; CONV: DW_TAG_compile_unit 34 ; CONV:[[SIG8:.]]: DW_TAG_base_type 35 ; CONV-NEXT:DW_AT_name {{.}}"DW_ATE_signed_8") 36 ; CONV-NEXT:DW_AT_encoding {{.}}DW_ATE_signed) 37 ; CONV-NEXT:DW_AT_byte_size {{.}}0x01) [all …]
/external/llvm-project/llvm/test/Transforms/AggressiveInstCombine/
D	trunc_select_cmp.ll	8 ; CHECK-NEXT: [[CONV:%.]] = sext i8 [[A:%.]] to i32 9 ; CHECK-NEXT: [[CMP:%.]] = icmp slt i32 [[CONV]], 109 10 ; CHECK-NEXT: [[COND:%.]] = select i1 [[CMP]], i32 109, i32 [[CONV]] 25 ; CHECK-NEXT: [[CONV:%.]] = sext i8 [[A:%.]] to i32 27 ; CHECK-NEXT: [[CMP:%.]] = icmp slt i32 [[CONV]], [[CONV2]] 28 ; CHECK-NEXT: [[COND:%.]] = select i1 [[CMP]], i32 [[CONV2]], i32 [[CONV]] 44 ; CHECK-NEXT: [[CONV:%.]] = zext i8 [[A:%.]] to i32 46 ; CHECK-NEXT: [[CMP:%.]] = icmp slt i32 [[CONV]], [[CONV2]] 47 ; CHECK-NEXT: [[COND:%.]] = select i1 [[CMP]], i32 [[CONV2]], i32 [[CONV]] 63 ; CHECK-NEXT: [[CONV:%.]] = zext i8 [[A:%.]] to i32 [all …]
D	trunc_select.ll	`109 ; CHECK-NEXT: [[CONV:%.]] = sext i8 [[A:%.]] to i16 110 ; CHECK-NEXT: [[SUB:%.]] = sub i16 0, [[CONV]] 111 ; CHECK-NEXT: [[SEL:%.]] = select i1 [[COND:%.]], i16 [[SUB]], i16 [[CONV]] 125 ; CHECK-NEXT: [[CONV:%.]] = zext i8 [[A:%.]] to i16 126 ; CHECK-NEXT: [[SUB:%.]] = sub i16 0, [[CONV]] 127 ; CHECK-NEXT: [[SEL:%.]] = select i1 [[COND:%.]], i16 [[SUB]], i16 [[CONV]]`
/external/llvm-project/llvm/test/Transforms/InstSimplify/
D	signed-div-rem.ll	14 ; CHECK-NEXT: [[CONV:%.]] = sext i8 %x to i32 15 ; CHECK-NEXT: [[DIV:%.]] = sdiv i32 [[CONV]], 128 34 ; CHECK-NEXT: [[CONV:%.]] = sext i8 %x to i32 35 ; CHECK-NEXT: [[DIV:%.]] = sdiv i32 [[CONV]], -128 54 ; CHECK-NEXT: [[CONV:%.]] = zext i8 %x to i32 55 ; CHECK-NEXT: [[DIV:%.]] = sdiv i32 [[CONV]], 255 74 ; CHECK-NEXT: [[CONV:%.]] = zext i8 %x to i32 75 ; CHECK-NEXT: [[DIV:%.]] = sdiv i32 [[CONV]], -255 165 ; CHECK-NEXT: [[CONV:%.*]] = sext i8 %x to i32 166 ; CHECK-NEXT: ret i32 [[CONV]] [all …]
/external/llvm-project/llvm/test/Transforms/PhaseOrdering/
D	two-shifts-by-sext.ll	32 ; CHECK-NEXT: [[CONV:%.]] = sext i8 [[LEN:%.]] to i32 33 ; CHECK-NEXT: [[SHL:%.]] = shl i32 [[VAL:%.]], [[CONV]] 34 ; CHECK-NEXT: [[SHR:%.]] = ashr i32 [[SHL]], [[CONV]] 53 ; CHECK-NEXT: [[CONV:%.]] = sext i8 [[LEN:%.]] to i32 54 ; CHECK-NEXT: [[SHL:%.]] = shl i32 [[VAL:%.]], [[CONV]] 55 ; CHECK-NEXT: [[SHR:%.]] = ashr i32 [[SHL]], [[CONV]] 76 ; CHECK-NEXT: [[CONV:%.]] = sext i8 [[LEN:%.]] to i32 77 ; CHECK-NEXT: call void @use_int32(i32 [[CONV]]) 78 ; CHECK-NEXT: [[SHL:%.]] = shl i32 [[VAL:%.]], [[CONV]] 79 ; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SHL]], [[CONV]] [all …]
D	reassociate-after-unroll.ll	`15 ; OLDPM-NEXT: [[CONV:%.]] = and i64 [[BLAH:%.]], 4294967295 32 ; OLDPM-NEXT: [[AND_EPIL]] = and i64 [[CONV]], [[K_05_EPIL]] 44 ; OLDPM-NEXT: [[AND]] = and i64 [[CONV]], [[K_05]] 62 ; NEWPM-NEXT: [[CONV:%.]] = and i64 [[BLAH:%.]], 4294967295 69 ; NEWPM-NEXT: [[AND_0:%.*]] = and i64 [[CONV]], 1 80 ; NEWPM-NEXT: [[AND_EPIL]] = and i64 [[CONV]], [[K_05_EPIL]] 104 ; NEWPM-NEXT: [[AND_1]] = and i64 [[CONV]], [[AND_PHI]]`
/external/llvm-project/llvm/test/Transforms/InstCombine/
D	strcmp-memcmp.ll	`16 ; CHECK-NEXT: [[CONV:%.]] = zext i1 [[CMP]] to i32 17 ; CHECK-NEXT: ret i32 [[CONV]] 33 ; CHECK-NEXT: [[CONV:%.]] = zext i1 [[CMP]] to i32 34 ; CHECK-NEXT: ret i32 [[CONV]] 48 ; CHECK-NEXT: [[CONV:%.]] = zext i1 [[CMP]] to i32 49 ; CHECK-NEXT: ret i32 [[CONV]] 63 ; CHECK-NEXT: [[CONV:%.]] = zext i1 [[CMP]] to i32 64 ; CHECK-NEXT: ret i32 [[CONV]] 78 ; CHECK-NEXT: [[CONV:%.*]] = zext i1 [[CMP]] to i32 79 ; CHECK-NEXT: ret i32 [[CONV]] [all …]`
D	double-float-shrink-1.ll	28 ; CHECK-NEXT: [[CONV:%.]] = fpext float [[F:%.]] to double 29 ; CHECK-NEXT: [[CALL:%.]] = call fast double @acos(double [[CONV]]) 51 ; CHECK-NEXT: [[CONV:%.]] = fpext float [[F:%.]] to double 52 ; CHECK-NEXT: [[CALL:%.]] = call fast double @acosh(double [[CONV]]) 75 ; CHECK-NEXT: [[CONV:%.]] = fpext float [[F:%.]] to double 76 ; CHECK-NEXT: [[CALL:%.]] = call fast double @asin(double [[CONV]]) 98 ; CHECK-NEXT: [[CONV:%.]] = fpext float [[F:%.]] to double 99 ; CHECK-NEXT: [[CALL:%.]] = call fast double @asinh(double [[CONV]]) 122 ; CHECK-NEXT: [[CONV:%.]] = fpext float [[F:%.]] to double 123 ; CHECK-NEXT: [[CALL:%.*]] = call fast double @atan(double [[CONV]]) [all …]
D	2011-05-28-swapmulsub.ll	`9 ; CHECK-NEXT: [[CONV:%.]] = add i16 [[TMP1]], -2 10 ; CHECK-NEXT: ret i16 [[CONV]] 28 ; CHECK-NEXT: [[CONV:%.]] = shl i16 [[SUBA_TR]], 2 29 ; CHECK-NEXT: ret i16 [[CONV]] 50 ; CHECK-NEXT: [[CONV:%.*]] = add i16 [[TMP1]], -28 51 ; CHECK-NEXT: ret i16 [[CONV]]`
D	select-cmp-cttz-ctlz.ll	`158 ; CHECK-NEXT: [[CONV:%.]] = zext i16 [[CT]] to i64 159 ; CHECK-NEXT: ret i64 [[CONV]] 171 ; CHECK-NEXT: [[CONV:%.]] = zext i32 [[CT]] to i64 172 ; CHECK-NEXT: ret i64 [[CONV]] 223 ; CHECK-NEXT: [[CONV:%.]] = trunc i64 [[CT]] to i16 224 ; CHECK-NEXT: ret i16 [[CONV]] 301 ; CHECK-NEXT: [[CONV:%.]] = zext i32 [[CT]] to i64 302 ; CHECK-NEXT: ret i64 [[CONV]] 314 ; CHECK-NEXT: [[CONV:%.*]] = trunc i32 [[CT]] to i16 315 ; CHECK-NEXT: ret i16 [[CONV]] [all …]`
D	sadd_sat.ll	45 ; CHECK-NEXT: [[CONV:%.]] = sext i32 [[A:%.]] to i64 47 ; CHECK-NEXT: [[ADD:%.]] = mul nsw i64 [[CONV1]], [[CONV]] 178 ; CHECK-NEXT: [[CONV:%.]] = sext i4 [[A:%.]] to i32 180 ; CHECK-NEXT: [[ADD:%.]] = add nsw i32 [[CONV1]], [[CONV]] 203 ; CHECK-NEXT: [[CONV:%.]] = sext i4 [[A:%.]] to i32 205 ; CHECK-NEXT: [[SUB:%.]] = sub nsw i32 [[CONV]], [[CONV1]] 324 ; CHECK-NEXT: [[CONV:%.]] = sext i32 [[A:%.]] to i64 326 ; CHECK-NEXT: [[ADD:%.]] = add nsw i64 [[CONV1]], [[CONV]] 351 ; CHECK-NEXT: [[CONV:%.]] = sext i32 [[A:%.]] to i64 353 ; CHECK-NEXT: [[ADD:%.*]] = add nsw i64 [[CONV1]], [[CONV]] [all …]
D	pr27343.ll	`10 ; CHECK-NEXT: [[CONV:%.*]] = zext i1 [[CMP]] to i32 11 ; CHECK-NEXT: ret i32 [[CONV]]`
/external/llvm/test/CodeGen/AMDGPU/
D	cvt_f32_ubyte.ll	`8 ; SI: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[LOADREG]] 9 ; SI: buffer_store_dword [[CONV]], 148 ; SI-NEXT: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[ADD]] 149 ; SI: buffer_store_dword [[CONV]], 192 ; SI: v_cvt_f32_ubyte0_e32 [[CONV:v[0-9]+]], [[VAL]] 193 ; SI: buffer_store_dword [[CONV]] 205 ; SI: v_cvt_f32_ubyte1_e32 [[CONV:v[0-9]+]], [[VAL]] 206 ; SI: buffer_store_dword [[CONV]] 219 ; SI: v_cvt_f32_ubyte2_e32 [[CONV:v[0-9]+]], [[VAL]] 220 ; SI: buffer_store_dword [[CONV]] [all …]`
/external/tensorflow/tensorflow/compiler/mlir/lite/tests/
D	dilated-conv.mlir	56 // CHECK-NEXT: [[CONV:%.]] = "tf.Conv2D" 89 …// CHECK-NEXT: [[CONV:%.]] = "tf.Conv2D"([[INPUT]], [[FILTER]]) {dilations = [1, 2, 2, 1], paddin… 90 …// CHECK-NEXT: [[RESULT:%.]] = "tf.BiasAdd"([[CONV]], [[BIAS]]) : (tensor<1x128x128x8xf32>, tenso… 107 …// CHECK-NEXT: [[CONV:%.]] = "tf.DepthwiseConv2dNative"([[INPUT]], [[FILTER]]) {dilations = [1, 2… 108 …// CHECK-NEXT: [[RESULT:%.]] = "tf.BiasAdd"([[CONV]], [[BIAS]]) : (tensor<1x128x128x8xf32>, tenso… 124 …// CHECK-NEXT: [[CONV:%.]] = "tf.Conv2D"([[INPUT]], [[FILTER]]) {dilations = [1, 2, 2, 1], paddin… 125 …// CHECK-NEXT: [[RESULT:%.]] = "tf.BiasAdd"([[CONV]], [[BIAS]]) : (tensor<1x128x128x8xf32>, tenso… 141 …// CHECK-NEXT: [[CONV:%.]] = "tf.DepthwiseConv2dNative"([[INPUT]], [[FILTER]]) {dilations = [1, 2… 142 …// CHECK-NEXT: [[RESULT:%.]] = "tf.BiasAdd"([[CONV]], [[BIAS]]) : (tensor<1x128x128x8xf32>, tenso… 163 …// CHECK-NEXT: [[CONV:%.]] = "tf.Conv2D"([[EXPAND]], [[FILTER]]) {dilations = [1, 2, 2, 1], paddi… [all …]
/external/llvm-project/llvm/test/Transforms/ExpandMemCmp/X86/
D	memcmp.ll	`591 ; ALL-NEXT: [[CONV:%.]] = zext i1 [[CMP]] to i32 592 ; ALL-NEXT: ret i32 [[CONV]] 618 ; X32-NEXT: [[CONV:%.]] = zext i1 [[CMP]] to i32 619 ; X32-NEXT: ret i32 [[CONV]] 642 ; X64_1LD-NEXT: [[CONV:%.]] = zext i1 [[CMP]] to i32 643 ; X64_1LD-NEXT: ret i32 [[CONV]] 662 ; X64_2LD-NEXT: [[CONV:%.]] = zext i1 [[CMP]] to i32 663 ; X64_2LD-NEXT: ret i32 [[CONV]] 680 ; ALL-NEXT: [[CONV:%.*]] = zext i1 [[CMP]] to i32 681 ; ALL-NEXT: ret i32 [[CONV]] [all …]`
/external/llvm-project/clang/test/utils/update_cc_test_checks/Inputs/
D	mangled_names.c.expected	`13 // CHECK-NEXT: [[CONV:%.]] = sext i32 [[TMP1]] to i64 14 // CHECK-NEXT: [[ADD:%.]] = add nsw i64 [[TMP0]], [[CONV]] 32 // CHECK-NEXT: [[CONV:%.]] = sext i32 [[TMP1]] to i64 33 // CHECK-NEXT: [[ADD:%.]] = add nsw i64 [[TMP0]], [[CONV]]`
D	mangled_names.c.funcsig.expected	`14 // CHECK-NEXT: [[CONV:%.]] = sext i32 [[TMP1]] to i64 15 // CHECK-NEXT: [[ADD:%.]] = add nsw i64 [[TMP0]], [[CONV]] 34 // CHECK-NEXT: [[CONV:%.]] = sext i32 [[TMP1]] to i64 35 // CHECK-NEXT: [[ADD:%.]] = add nsw i64 [[TMP0]], [[CONV]]`
/external/mesa3d/src/mesa/main/
D	format_utils.c	845 #define SWIZZLE_CONVERT_LOOP(DST_TYPE, DST_CHANS, SRC_TYPE, SRC_CHANS, CONV) \ argument 851 tmp[j] = CONV; \ 887 #define SWIZZLE_CONVERT(DST_TYPE, SRC_TYPE, CONV) \ argument 902 SWIZZLE_CONVERT_LOOP(DST_TYPE, 1, SRC_TYPE, 1, CONV); \ 905 SWIZZLE_CONVERT_LOOP(DST_TYPE, 1, SRC_TYPE, 2, CONV); \ 908 SWIZZLE_CONVERT_LOOP(DST_TYPE, 1, SRC_TYPE, 3, CONV); \ 911 SWIZZLE_CONVERT_LOOP(DST_TYPE, 1, SRC_TYPE, 4, CONV); \ 918 SWIZZLE_CONVERT_LOOP(DST_TYPE, 2, SRC_TYPE, 1, CONV); \ 921 SWIZZLE_CONVERT_LOOP(DST_TYPE, 2, SRC_TYPE, 2, CONV); \ 924 SWIZZLE_CONVERT_LOOP(DST_TYPE, 2, SRC_TYPE, 3, CONV); \ [all …]
/external/llvm-project/llvm/test/Transforms/TypePromotion/ARM/
D	signed.ll	`27 ; CHECK-NEXT: [[CONV:%.]] = zext i1 [[CMP]] to i16 28 ; CHECK-NEXT: ret i16 [[CONV]] 40 ; CHECK-NEXT: [[CONV:%.]] = zext i1 [[CMP]] to i16 41 ; CHECK-NEXT: ret i16 [[CONV]] 53 ; CHECK-NEXT: [[CONV:%.*]] = zext i1 [[CMP]] to i16 54 ; CHECK-NEXT: ret i16 [[CONV]]`
/external/tensorflow/tensorflow/compiler/mlir/lite/quantization/tensorflow/tests/
D	tf_to_quant.mlir	`85 // CHECK: %[[CONV:.]] = "tf.Conv2D"(%arg0, %[[DEQUANTIZE]]) 86 // CHECK: return %[[CONV]] 106 // CHECK: %[[CONV:.]] = "tf.Conv2D"(%arg0, %[[DEQUANTIZE]]) 107 // CHECK: return %[[CONV]] : tensor<256x8x7x16xf32> 125 // CHECK: %[[CONV:.]] = "tf.DepthwiseConv2dNative"(%arg0, %[[DEQUANTIZE]]) 126 // CHECK: return %[[CONV]] 146 // CHECK: %[[CONV:.]] = "tf.DepthwiseConv2dNative"(%arg0, %[[DEQUANTIZE]]) 147 // CHECK: return %[[CONV]]`
/external/llvm-project/clang/test/CodeGenObjC/
D	matrix-type-operators.m	`19 // CHECK-NEXT: [[CONV:%.]] = sext i32 [[CALL]] to i64 27 // CHECK-NEXT: [[IDX2:%.]] = add i64 [[IDX1]], [[CONV]] 46 // CHECK-NEXT: [[CONV:%.]] = sext i32 [[CALL]] to i64 57 // CHECK-NEXT: [[IDX2:%.]] = add i64 [[IDX1]], [[CONV]]`
/external/llvm-project/llvm/test/Transforms/SCCP/
D	resolvedundefsin-tracked-fn.ll	14 ; CHECK-NEXT: [[CONV:%.]] = trunc i32 [[H]] to i8 15 ; CHECK-NEXT: [[CALL:%.]] = call i32 @test1_k(i8 [[CONV]], i32 0) 40 ; CHECK-NEXT: [[CONV:%.]] = sext i32 [[TMP0]] to i64 41 ; CHECK-NEXT: [[TMP1:%.]] = inttoptr i64 [[CONV]] to %t1* 91 ; CHECK-NEXT: [[CONV:%.]] = trunc i32 [[H]] to i8 92 ; CHECK-NEXT: [[CALL:%.]] = call i32 @test2_k(i8 [[CONV]], i32 0) 117 ; CHECK-NEXT: [[CONV:%.]] = sext i32 [[TMP0]] to i64 118 ; CHECK-NEXT: [[TMP1:%.]] = inttoptr i64 [[CONV]] to %t1* 170 ; CHECK-NEXT: [[CONV:%.]] = trunc i32 [[H]] to i8 171 ; CHECK-NEXT: [[CALL:%.]] = call i32 @test3_k(i8 [[CONV]], i32 0) [all …]
/external/llvm-project/llvm/test/Transforms/SLPVectorizer/X86/
D	cse.ll	70 ; CHECK-NEXT: [[CONV:%.]] = sitofp i32 [[N:%.]] to double 77 ; CHECK-NEXT: [[TMP3:%.]] = insertelement <4 x double> undef, double [[CONV]], i32 0 78 ; CHECK-NEXT: [[TMP4:%.]] = insertelement <4 x double> [[TMP3]], double [[CONV]], i32 1 79 ; CHECK-NEXT: [[TMP5:%.]] = insertelement <4 x double> [[TMP4]], double [[CONV]], i32 2 80 ; CHECK-NEXT: [[TMP6:%.]] = insertelement <4 x double> [[TMP5]], double [[CONV]], i32 3 204 ; CHECK-NEXT: [[CONV:%.]] = sitofp i32 [[N:%.]] to double 211 ; CHECK-NEXT: [[TMP3:%.]] = insertelement <4 x double> undef, double [[CONV]], i32 0 212 ; CHECK-NEXT: [[TMP4:%.]] = insertelement <4 x double> [[TMP3]], double [[CONV]], i32 1 213 ; CHECK-NEXT: [[TMP5:%.]] = insertelement <4 x double> [[TMP4]], double [[CONV]], i32 2 214 ; CHECK-NEXT: [[TMP6:%.]] = insertelement <4 x double> [[TMP5]], double [[CONV]], i32 3 [all …]
/external/tensorflow/tensorflow/compiler/mlir/tensorflow/tests/
D	layout_optimization_to_nchw.mlir	`26 // CHECK: %[[CONV:[0-9]*]] = "tf.Conv2D"(%arg0, %arg1) 30 // CHECK: return %[[CONV]]`
/external/llvm/test/Transforms/InstSimplify/
D	shift-128-kb.ll	`9 ; CHECK: [[CONV:%.]] = zext i32 %IntegerBitWidth to i64 10 ; CHECK-NEXT: [[SUB:%.]] = sub i64 128, [[CONV]]`

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