| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/ |
| D | X86GenRegisterInfo.inc | 6293 false, /* HasDisjunctSubRegs */
6305 false, /* HasDisjunctSubRegs */
6317 false, /* HasDisjunctSubRegs */
6329 false, /* HasDisjunctSubRegs */
6341 false, /* HasDisjunctSubRegs */
6353 false, /* HasDisjunctSubRegs */
6365 true, /* HasDisjunctSubRegs */
6377 true, /* HasDisjunctSubRegs */
6389 false, /* HasDisjunctSubRegs */
6401 false, /* HasDisjunctSubRegs */
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenRegisterInfo.inc | 4801 true, /* HasDisjunctSubRegs */
4813 false, /* HasDisjunctSubRegs */
4825 false, /* HasDisjunctSubRegs */
4837 false, /* HasDisjunctSubRegs */
4849 false, /* HasDisjunctSubRegs */
4861 false, /* HasDisjunctSubRegs */
4873 false, /* HasDisjunctSubRegs */
4885 false, /* HasDisjunctSubRegs */
4897 false, /* HasDisjunctSubRegs */
4909 false, /* HasDisjunctSubRegs */
[all …]
|
| /external/llvm-project/llvm/test/TableGen/ |
| D | ConcatenatedSubregs.td | 102 // CHECK: HasDisjunctSubRegs: 1
107 // CHECK: HasDisjunctSubRegs: 1
120 // CHECK: HasDisjunctSubRegs: 1
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/ |
| D | ARMGenRegisterInfo.inc | 6551 false, /* HasDisjunctSubRegs */
6563 true, /* HasDisjunctSubRegs */
6575 false, /* HasDisjunctSubRegs */
6587 true, /* HasDisjunctSubRegs */
6599 false, /* HasDisjunctSubRegs */
6611 false, /* HasDisjunctSubRegs */
6623 false, /* HasDisjunctSubRegs */
6635 false, /* HasDisjunctSubRegs */
6647 false, /* HasDisjunctSubRegs */
6659 false, /* HasDisjunctSubRegs */
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenRegisterInfo.inc | 6899 false, /* HasDisjunctSubRegs */
6911 false, /* HasDisjunctSubRegs */
6923 false, /* HasDisjunctSubRegs */
6935 false, /* HasDisjunctSubRegs */
6947 false, /* HasDisjunctSubRegs */
6959 false, /* HasDisjunctSubRegs */
6971 false, /* HasDisjunctSubRegs */
6983 false, /* HasDisjunctSubRegs */
6995 false, /* HasDisjunctSubRegs */
7007 false, /* HasDisjunctSubRegs */
[all …]
|
| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/ |
| D | PPCGenRegisterInfo.inc | 4375 false, /* HasDisjunctSubRegs */
4387 false, /* HasDisjunctSubRegs */
4399 false, /* HasDisjunctSubRegs */
4411 false, /* HasDisjunctSubRegs */
4423 false, /* HasDisjunctSubRegs */
4435 false, /* HasDisjunctSubRegs */
4447 true, /* HasDisjunctSubRegs */
4459 false, /* HasDisjunctSubRegs */
4471 false, /* HasDisjunctSubRegs */
4483 false, /* HasDisjunctSubRegs */
[all …]
|
| /external/llvm-project/llvm/utils/TableGen/ |
| D | CodeGenRegisters.h | 156 bool HasDisjunctSubRegs; member
338 bool HasDisjunctSubRegs; variable
|
| D | CodeGenRegisters.cpp | 161 HasDisjunctSubRegs(false), in CodeGenRegister()
273 HasDisjunctSubRegs = ExplicitSubRegs.size() > 1; in computeSubRegs()
296 HasDisjunctSubRegs |= ESR->HasDisjunctSubRegs; in computeSubRegs()
2115 RC.HasDisjunctSubRegs = false; in computeDerivedInfo()
2118 RC.HasDisjunctSubRegs |= Reg->HasDisjunctSubRegs; in computeDerivedInfo()
|
| D | RegisterInfoEmitter.cpp | 1420 << (RC.HasDisjunctSubRegs?"true":"false") in runTargetDesc()
1655 OS << "\tHasDisjunctSubRegs: " << RC.HasDisjunctSubRegs << '\n'; in debugDump()
1687 OS << "\tHasDisjunctSubRegs: " << R.HasDisjunctSubRegs << '\n'; in debugDump()
|
| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.h | 131 bool HasDisjunctSubRegs; member
312 bool HasDisjunctSubRegs; variable
|
| D | CodeGenRegisters.cpp | 111 HasDisjunctSubRegs(false), in CodeGenRegister()
221 HasDisjunctSubRegs = ExplicitSubRegs.size() > 1; in computeSubRegs()
243 HasDisjunctSubRegs |= SR->HasDisjunctSubRegs; in computeSubRegs()
1834 RC.HasDisjunctSubRegs = false; in computeDerivedInfo()
1837 RC.HasDisjunctSubRegs |= Reg->HasDisjunctSubRegs; in computeDerivedInfo()
|
| D | RegisterInfoEmitter.cpp | 1330 << (RC.HasDisjunctSubRegs?"true":"false") in runTargetDesc()
|
| /external/llvm/include/llvm/Target/ |
| D | TargetRegisterInfo.h | 72 const bool HasDisjunctSubRegs; variable
|
| /external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 59 const bool HasDisjunctSubRegs; variable
|
| D | MachineRegisterInfo.h | 215 return subRegLivenessEnabled() && RC.HasDisjunctSubRegs; in shouldTrackSubRegLiveness()
|
| /external/llvm-project/llvm/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 60 const bool HasDisjunctSubRegs; variable
|
| D | MachineRegisterInfo.h | 215 return subRegLivenessEnabled() && RC.HasDisjunctSubRegs; in shouldTrackSubRegLiveness()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | MachineRegisterInfo.h | 192 return subRegLivenessEnabled() && RC.HasDisjunctSubRegs; in shouldTrackSubRegLiveness()
|
| /external/llvm-project/llvm/lib/CodeGen/ |
| D | ScheduleDAGInstrs.cpp | 373 if (!RC.HasDisjunctSubRegs) in getLaneMaskForMO()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| D | ScheduleDAGInstrs.cpp | 371 if (!RC.HasDisjunctSubRegs) in getLaneMaskForMO()
|
| /external/llvm/lib/CodeGen/ |
| D | ScheduleDAGInstrs.cpp | 406 if (!RC.HasDisjunctSubRegs) in getLaneMaskForMO()
|
| /external/llvm-project/llvm/lib/Target/AArch64/ |
| D | AArch64LoadStoreOptimizer.cpp | 1301 if (RegClass->HasDisjunctSubRegs) { in canRenameUpToDef()
|