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Searched refs:MCR (Results 1 – 25 of 52) sorted by relevance

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/external/arm-neon-tests/
DInitCache.s24 MCR p15, 0, r0, c1, c0, 0 ; write CP15 register 1
36 MCR p15, 0, r0, c1, c0, 1 ; Write Auxiliary Control Register
45 MCR p15, 0, r0, c1, c0, 0 ; write CP15 register 1
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/ARM/
DARMGenRegisterInfo.inc5905 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::HPRRegClassID];
5907 makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5923 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::SPRRegClassID];
5925 makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5942 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::GPRRegClassID];
5944 makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5961 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::GPRwithAPSRRegClassID];
5963 makeArrayRef(MCR.begin(), MCR.getNumRegs()),
5979 const MCRegisterClass &MCR = ARMMCRegisterClasses[ARM::GPRwithZRRegClassID];
5981 makeArrayRef(MCR.begin(), MCR.getNumRegs()),
[all …]
DARMGenAsmWriter.inc1454 808570991U, // MCR
5678 74531720U, // MCR
9233 // CDP, LDRD_POST, LDRD_PRE, MCR, MRC, MVE_SQRSHRL, MVE_UQRSHLL, MVE_VMOV...
10333 // CDP, MCR, MCRR, MSR, VABSD, VADDD, VCMPD, VCMPED, VDIVD, VMOVD, VMULD,...
10947 // MCR, MCRR, VADDD, VDIVD, VMULD, VNMULD, VSUBD, t2MCR, t2MCR2, t2MCRR, ...
11139 // MCR, MCRR, t2MCR, t2MCR2, t2MCRR, t2MCRR2
11290 // MCR, t2MCR, t2MCR2
/external/crosvm/devices/src/
Dserial.rs23 const MCR: u8 = 4; constant
301 MCR => self.modem_control = v, in handle_write()
348 MCR => self.modem_control, in read()
/external/llvm/test/MC/Disassembler/ARM/
Dinvalid-armv7.txt155 # Opcode=171 Name=MCR Format=ARM_FORMAT_BRFRM(2)
161 # Encoding error: coproc == 10 or 11 for MCR[R]/MR[R]C
Dthumb2.txt1020 # MCR/MCR2
/external/llvm-project/llvm/test/MC/Disassembler/ARM/
Dinvalid-armv7.txt178 # Opcode=171 Name=MCR Format=ARM_FORMAT_BRFRM(2)
184 # Encoding error: coproc == 10 or 11 for MCR[R]/MR[R]C
Dbasic-arm-instructions.txt709 # MCR/MCR2
Dthumb2.txt1020 # MCR/MCR2
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/PowerPC/
DPPCGenRegisterInfo.inc4278 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::GPRCRegClassID];
4280 makeArrayRef(MCR.begin(), MCR.getNumRegs()),
4294 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::GPRC_NOR0RegClassID];
4296 makeArrayRef(MCR.begin(), MCR.getNumRegs()),
4310 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::GPRC_and_GPRC_NOR0RegClassID];
4312 makeArrayRef(MCR.begin(), MCR.getNumRegs()),
4326 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8RCRegClassID];
4328 makeArrayRef(MCR.begin(), MCR.getNumRegs()),
4342 const MCRegisterClass &MCR = PPCMCRegisterClasses[PPC::G8RC_NOX0RegClassID];
4344 makeArrayRef(MCR.begin(), MCR.getNumRegs()),
[all …]
/external/OpenCSD/decoder/tests/snapshots/TC2/ds5-dumps/
Dptmv1_0x13.txt524 Instruction 491 S:0xC0012246 0xEE013E90 0 MCR p14,#0x0,r3,c1,c0,#4 false
528 Instruction 494 S:0xC0012250 0xEE003E17 0 MCR p14,#0x0,r3,c0,c7,#0 false
555 Instruction 520 S:0xC0011EA8 0xEE001EB0 0 MCR p14,#0x0,r1,c0,c0,#5 false
571 Instruction 535 S:0xC0011F08 0xEE001E90 0 MCR p14,#0x0,r1,c0,c0,#4 false
588 Instruction 551 S:0xC0011EA2 0xEE001EB1 0 MCR p14,#0x0,r1,c0,c1,#5 false
604 Instruction 566 S:0xC0011F02 0xEE001E91 0 MCR p14,#0x0,r1,c0,c1,#4 false
621 Instruction 582 S:0xC0011E9C 0xEE001EB2 0 MCR p14,#0x0,r1,c0,c2,#5 false
637 Instruction 597 S:0xC0011EFC 0xEE001E92 0 MCR p14,#0x0,r1,c0,c2,#4 false
654 Instruction 613 S:0xC0011E96 0xEE001EB3 0 MCR p14,#0x0,r1,c0,c3,#5 false
670 Instruction 628 S:0xC0011EF6 0xEE001E93 0 MCR p14,#0x0,r1,c0,c3,#4 false
[all …]
Detmv3_0x10.txt832 Instruction 774 S:0xC000CE7A 0xEE01CF10 1 MCR p15,#0x0,r12,c1,c0,#0 false
1017 Instruction 949 S:0xC000CE7A 0xEE01CF10 1 MCR p15,#0x0,r12,c1,c0,#0 false
2711 Instruction 2566 S:0xC00176CC 0xEE023F10 4 MCR p15,#0x0,r3,c2,c0,#0 false
2748 Instruction 2602 S:0xC0017ACC 0xEE0D1F30 1 MCR p15,#0x0,r1,c13,c0,#1 false
2751 Instruction 2604 S:0xC0017AD4 0xEE020F10 26 MCR p15,#0x0,r0,c2,c0,#0 false
2762 Instruction 2612 S:0xC000CD0A 0xEE0D3F70 1 MCR p15,#0x0,r3,c13,c0,#3 false
2764 Instruction 2614 S:0xC000CD12 0xEE0D4F50 1 MCR p15,#0x0,r4,c13,c0,#2 false
2928 Instruction 2769 S:0xC000CB38 0xEE010F10 1 MCR p15,#0x0,r0,c1,c0,#0 false
3043 Instruction 2878 S:0xC000CAD8 0xEE010F10 1 MCR p15,#0x0,r0,c1,c0,#0 false
6532 Instruction 6232 S:0xC000CAD8 0xEE010F10 1 MCR p15,#0x0,r0,c1,c0,#0 false
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/AArch64/
DAArch64GenRegisterInfo.inc6812 const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR32RegClassID];
6814 makeArrayRef(MCR.begin(), MCR.getNumRegs()),
6826 const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR32spRegClassID];
6828 makeArrayRef(MCR.begin(), MCR.getNumRegs()),
6840 const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR32commonRegClassID];
6842 makeArrayRef(MCR.begin(), MCR.getNumRegs()),
6854 const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR64RegClassID];
6856 makeArrayRef(MCR.begin(), MCR.getNumRegs()),
6868 const MCRegisterClass &MCR = AArch64MCRegisterClasses[AArch64::GPR64spRegClassID];
6870 makeArrayRef(MCR.begin(), MCR.getNumRegs()),
[all …]
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/
DMipsGenRegisterInfo.inc4767 const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR32RegClassID];
4769 makeArrayRef(MCR.begin(), MCR.getNumRegs()),
4784 const MCRegisterClass &MCR = MipsMCRegisterClasses[Mips::FGR64RegClassID];
4786 makeArrayRef(MCR.begin(), MCR.getNumRegs()),
/external/llvm/test/MC/ARM/
Ddiagnostics.s140 @ Out of range immediate for MCR/MCR2/MCRR/MCRR2
/external/capstone/arch/ARM/
DARMGenAsmWriter.inc222 2197858686U, // MCR
3026 2311712U, // MCR
6141 // CDP, LDRD_POST, LDRD_PRE, MCR, MRC, STRD_POST, STRD_PRE, VLD4DUPd16, V...
7105 // CDP, MCR, MCRR, MRRC, MSR, VABDfd, VABDfq, VABSD, VABSS, VABSfd, VABSf...
7276 // CDP, MCR, MCRR, MRRC, VABDfd, VABDfq, VACGEd, VACGEq, VACGTd, VACGTq, ...
7677 // MCR, MCRR, MRRC, VABDfd, VABDfq, VACGEd, VACGEq, VACGTd, VACGTq, VADDD...
7871 // MCR, MCRR, MRRC, t2MCR, t2MCR2, t2MCRR, t2MCRR2, t2MRRC, t2MRRC2
8026 // MCR, t2MCR, t2MCR2
8929 // (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn, c_imm:$CRm, 0, pred:$p)
/external/llvm-project/llvm/test/MC/ARM/
Ddiagnostics.s156 @ Out of range immediate for MCR/MCR2/MCRR/MCRR2
Dbasic-thumb2-instructions.s1525 @ MCR/MCR2
1531 MCR P7, #1, R5, C1, C1, #4
1533 MCR P14, #0, R4, C0, C5
Dbasic-arm-instructions.s1243 @ MCR/MCR2
1247 MCR P7, #1, R5, C1, C1, #4
/external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/X86/
DX86GenRegisterInfo.inc6260 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8RegClassID];
6262 makeArrayRef(MCR.begin(), MCR.getNumRegs()),
6276 const MCRegisterClass &MCR = X86MCRegisterClasses[X86::GR8_NOREXRegClassID];
6278 makeArrayRef(MCR.begin(), MCR.getNumRegs()),
/external/llvm/lib/Target/ARM/
DARMInstrInfo.td5049 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
5055 ComplexDeprecationPredicate<"MCR">;
5057 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5530 // Pre-v7 uses MCR for synchronization barriers.
5531 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrInfo.td5404 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
5410 ComplexDeprecationPredicate<"MCR">;
5412 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
5902 // Pre-v7 uses MCR for synchronization barriers.
5903 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
DARMScheduleA57.td145 "(t2)?MCR(2|R|R2)?$", "(t2)?MRC(2)?$",
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrInfo.td5554 def MCR : MovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
5560 ComplexDeprecationPredicate<"MCR">;
5562 (MCR p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
6053 // Pre-v7 uses MCR for synchronization barriers.
6054 def : ARMPat<(ARMMemBarrierMCR GPR:$zero), (MCR 15, 0, GPR:$zero, 7, 10, 5)>,
DARMScheduleA57.td133 "(t2)?MCR(2|R|R2)?$", "(t2)?MRC(2)?$",

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