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/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dllvm.amdgcn.ds.fmax.ll7 …struction-select -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX8-MIR %s
8 …struction-select -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GFX9-MIR %s
28 ; GFX8-MIR-LABEL: name: ds_fmax_f32_ss
29 ; GFX8-MIR: bb.1 (%ir-block.0):
30 ; GFX8-MIR: liveins: $sgpr2, $sgpr3
31 ; GFX8-MIR: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2
32 ; GFX8-MIR: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3
33 ; GFX8-MIR: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
34 ; GFX8-MIR: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
35 ; GFX8-MIR: $m0 = S_MOV_B32 -1
[all …]
/external/llvm-project/llvm/test/CodeGen/NVPTX/
Dproxy-reg-erasure-mir.ll2 ; RUN: | FileCheck %s --check-prefix=MIR --check-prefix=MIR-BEFORE
5 ; RUN: | FileCheck %s --check-prefix=MIR --check-prefix=MIR-AFTER
7 ; Check ProxyRegErasure pass MIR manipulation.
11 ; MIR: body:
12 ; MIR-DAG: Callseq_Start {{[0-9]+}}, {{[0-9]+}}
13 ; MIR-DAG: %0:int32regs, %1:int32regs, %2:int32regs, %3:int32regs = LoadParamMemV4I32 0
14 ; MIR-DAG: Callseq_End {{[0-9]+}}
16 ; MIR-BEFORE-DAG: %4:int32regs = ProxyRegI32 killed %0
17 ; MIR-BEFORE-DAG: %5:int32regs = ProxyRegI32 killed %1
18 ; MIR-BEFORE-DAG: %6:int32regs = ProxyRegI32 killed %2
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/
Dirtranslator-stackprotect-check.ll2 …anslator -verify-machineinstrs -global-isel %s -o - | FileCheck --check-prefixes CHECK,CHECK-MIR %s
28 ; CHECK-MIR: bb.1.entry:
29 ; CHECK-MIR: %0:_(p0) = G_FRAME_INDEX %stack.0.StackGuardSlot
30 ; CHECK-MIR-NEXT: %1:gpr64sp(p0) = LOAD_STACK_GUARD :: (dereferenceable invariant load 8 from @__…
31 ; CHECK-MIR-NEXT: %2:gpr64sp(p0) = LOAD_STACK_GUARD :: (dereferenceable invariant load 8 from @__…
32 ; CHECK-MIR-NEXT: G_STORE %2(p0), %0(p0) :: (volatile store 8 into %stack.0.StackGuardSlot)
33 ; CHECK-MIR-NEXT: %3:_(p0) = G_FRAME_INDEX %stack.1.buf
34 ; CHECK-MIR-NEXT: %4:gpr64sp(p0) = LOAD_STACK_GUARD :: (dereferenceable invariant load 8 from @__…
35 ; CHECK-MIR-NEXT: %5:_(p0) = G_LOAD %0(p0) :: (volatile dereferenceable load 8 from %ir.StackGuar…
36 ; CHECK-MIR-NEXT: %6:_(s1) = G_ICMP intpred(eq), %4(p0), %5
[all …]
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Daix-lower-constant-pool-index.ll3 ; RUN: --check-prefix=32SMALL-MIR %s
7 ; RUN: --check-prefix=32LARGE-MIR %s
11 ; RUN: --check-prefix=64SMALL-MIR %s
15 ; RUN: --check-prefix=64LARGE-MIR %s
34 ; 32SMALL-MIR: renamable $r[[REG1:[0-9]+]] = LWZtoc %const.0, $r2 :: (load 4 from got)
35 ; 32SMALL-MIR: renamable $f[[REG2:[0-9]+]] = LFS 0, killed renamable $r[[REG1]] :: (load 4 from con…
37 ; 32LARGE-MIR: renamable $r[[REG1:[0-9]+]] = ADDIStocHA $r2, %const.0
38 ; 32LARGE-MIR: renamable $r[[REG2:[0-9]+]] = LWZtocL %const.0, killed renamable $r[[REG1]], implici…
39 ; 32LARGE-MIR: renamable $f[[REG3:[0-9]+]] = LFS 0, killed renamable $r[[REG2]] :: (load 4 from con…
41 ; 64SMALL-MIR: renamable $x[[REG1:[0-9]+]] = LDtocCPT %const.0, $x2 :: (load 8 from got)
[all …]
Daix-lower-jump-table.ll3 ; RUN: --check-prefix=32SMALL-MIR %s
7 ; RUN: --check-prefix=32LARGE-MIR %s
11 ; RUN: --check-prefix=64SMALL-MIR %s
15 ; RUN: --check-prefix=64LARGE-MIR %s
65 ; 32SMALL-MIR: renamable $r[[REG1:[0-9]+]] = LWZtoc %jump-table.0, $r2 :: (load 4 from got)
66 ; 32SMALL-MIR: renamable $r[[REG3:[0-9]+]] = RLWINM killed renamable $r[[REG2:[0-9]+]], 2, 0, 29
67 ; 32SMALL-MIR: renamable $r[[REG4:[0-9]+]] = LWZX killed renamable $r[[REG3]], renamable $r[[REG1]]…
68 ; 32SMALL-MIR: renamable $r[[REG5:[0-9]+]] = ADD4 killed renamable $r[[REG4]], killed renamable $r[…
70 ; 32LARGE-MIR: renamable $r[[REG1:[0-9]+]] = ADDIStocHA $r2, %jump-table.0
71 ; 32LARGE-MIR: renamable $r[[REG2:[0-9]+]] = LWZtocL %jump-table.0, killed renamable $r[[REG1]], im…
[all …]
Daix-lower-block-address.ll3 ; RUN: --check-prefix=32SMALL-MIR %s
7 ; RUN: --check-prefix=32LARGE-MIR %s
11 ; RUN: --check-prefix=64SMALL-MIR %s
15 ; RUN: --check-prefix=64LARGE-MIR %s
39 ; 32SMALL-MIR: renamable $r[[REG1:[0-9]+]] = LWZtoc blockaddress(@foo, %ir-block.__here), $r2 :: (l…
41 ; 32LARGE-MIR: renamable $r[[REG1:[0-9]+]] = ADDIStocHA $r2, blockaddress(@foo, %ir-block.__here)
42 ; 32LARGE-MIR: renamable $r[[REG2:[0-9]+]] = LWZtocL blockaddress(@foo, %ir-block.__here), killed r…
44 ; 64SMALL-MIR: renamable $x[[REG1:[0-9]+]] = LDtocBA blockaddress(@foo, %ir-block.__here), $x2 :: (…
46 ; 64LARGE-MIR: renamable $x[[REG1:[0-9]+]] = ADDIStocHA8 $x2, blockaddress(@foo, %ir-block.__here)
47 ; 64LARGE-MIR: renamable $x[[REG2:[0-9]+]] = LDtocL blockaddress(@foo, %ir-block.__here), killed re…
Daix-sret-param.ll3 ; RUN: --check-prefixes=MIR,MIR32 %s
7 ; RUN: --check-prefixes=MIR,MIR64 %s
35 ; MIR: name: test1
36 ; MIR: stack:
37 ; MIR-NEXT: - { id: 0, name: s, type: default, offset: 0, size: 1, alignment: 8,
68 ; MIR: name: test2
69 ; MIR: stack:
70 ; MIR-NEXT: - { id: 0, name: t, type: default, offset: 0, size: 24, alignment: 8,
Dfp-strict-conv.ll10 ; RUN: -stop-after=machine-cp | FileCheck %s -check-prefix=MIR
332 ; MIR-LABEL: name: fptoint_nofpexcept_f64
333 ; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPSXWS
334 ; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPUXWS
335 ; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPSXDS
336 ; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPUXDS
350 ; MIR-LABEL: name: fptoint_nofpexcept_f32
351 ; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPSXWS
352 ; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPUXWS
353 ; MIR: renamable $f{{[0-9]+}} = nofpexcept XSCVDPSXDS
[all …]
/external/llvm-project/llvm/test/Transforms/SampleProfile/
Dpseudo-probe-emit.ll4 …-probe-for-profiling -stop-after=pseudo-probe-inserter -o - | FileCheck %s --check-prefix=CHECK-MIR
12 ; CHECK-MIR: PSEUDO_PROBE [[#GUID:]], 1, 0, 0
17 ; CHECK-MIR: PSEUDO_PROBE [[#GUID]], 3, 0, 0
18 ; CHECK-MIR: PSEUDO_PROBE [[#GUID]], 4, 0, 0
23 ; CHECK-MIR: PSEUDO_PROBE [[#GUID]], 2, 0, 0
24 ; CHECK-MIR: PSEUDO_PROBE [[#GUID]], 4, 0, 0
37 ; CHECK-MIR: PSEUDO_PROBE [[#GUID2:]], 1, 0, 0
40 ; CHECK-MIR: PSEUDO_PROBE [[#GUID2]], 2, 1, 0
44 ; CHECK-MIR: PSEUDO_PROBE [[#GUID2]], 3, 2, 0
/external/llvm-project/llvm/unittests/Target/WebAssembly/
DWebAssemblyExceptionInfoTest.cpp43 std::unique_ptr<MIRParser> &MIR, in parseMIR() argument
48 MIR = createMIRParser(std::move(MBuffer), Context); in parseMIR()
49 if (!MIR) in parseMIR()
52 std::unique_ptr<Module> M = MIR->parseIRModule(); in parseMIR()
58 if (MIR->parseMachineFunctions(*M, MMI)) in parseMIR()
157 std::unique_ptr<MIRParser> MIR; in TEST() local
160 parseMIR(Context, MIR, *TM, MIRString, "test0", MMI); in TEST()
332 std::unique_ptr<MIRParser> MIR; in TEST() local
335 parseMIR(Context, MIR, *TM, MIRString, "test1", MMI); in TEST()
/external/llvm-project/llvm/unittests/CodeGen/GlobalISel/
DGISelMITest.h57 std::unique_ptr<MIRParser> &MIR, in parseMIR() argument
63 MIR = createMIRParser(std::move(MBuffer), Context); in parseMIR()
64 if (!MIR) in parseMIR()
67 std::unique_ptr<Module> M = MIR->parseIRModule(); in parseMIR()
73 if (MIR->parseMachineFunctions(*M, MMI)) in parseMIR()
81 std::unique_ptr<MIRParser> MIR; in createDummyModule() local
84 parseMIR(Context, MIR, TM, MIRString, FuncName, *MMI); in createDummyModule()
/external/llvm/unittests/MI/
DLiveIntervalTest.cpp53 legacy::PassManagerBase &PM, std::unique_ptr<MIRParser> &MIR, in parseMIR() argument
57 MIR = createMIRParser(std::move(MBuffer), Context); in parseMIR()
58 if (!MIR) in parseMIR()
61 std::unique_ptr<Module> M = MIR->parseLLVMModule(); in parseMIR()
73 LLVMTM.addMachineFunctionAnalysis(PM, MIR.get()); in parseMIR()
150 std::unique_ptr<MIRParser> MIR; in liveIntervalTest() local
151 std::unique_ptr<Module> M = parseMIR(Context, PM, MIR, *TM, MIRString, in liveIntervalTest()
/external/llvm/docs/
DMIRLangRef.rst2 Machine IR (MIR) Format Reference Manual
14 This document is a reference manual for the Machine IR (MIR) serialization
15 format. MIR is a human readable serialization format that is used to represent
19 The MIR serialization format is designed to be used for testing the code
25 The MIR serialization format uses a YAML container. YAML is a standard
30 A MIR file is split up into a series of `YAML documents`_. The first document
36 MIR Testing Guide
39 You can use the MIR format for testing in two different ways:
41 - You can write MIR tests that invoke a single code generation pass using the
45 tests and check the MIR output of a specific code generation pass.
[all …]
/external/llvm-project/llvm/docs/
DMIRLangRef.rst2 Machine IR (MIR) Format Reference Manual
14 This document is a reference manual for the Machine IR (MIR) serialization
15 format. MIR is a human readable serialization format that is used to represent
19 The MIR serialization format is designed to be used for testing the code
25 The MIR serialization format uses a YAML container. YAML is a standard
30 A MIR file is split up into a series of `YAML documents`_. The first document
36 MIR Testing Guide
39 You can use the MIR format for testing in two different ways:
41 - You can write MIR tests that invoke a single code generation pass using the
45 tests and check the MIR output of a specific code generation pass.
[all …]
/external/llvm-project/llvm/test/DebugInfo/MIR/AArch64/
Ddbgcall-site-indirect-param-with-offset.mir2 # RUN: | FileCheck %s -check-prefix=MIR
9 # MIR: renamable $w0 = LDRWui killed renamable $x8
10 # MIR-NOT: DBG_VALUE $x0, 0, {{.*}}, !DIExpression(DW_OP_LLVM_entry_value
11 # MIR-NEXT: BL @baz
12 # MIR-NEXT: frame-destroy LDPXpost
13 # MIR-NEXT: TCRETURNdi @baz
Ddbgcall-site-indirect-param.mir2 # RUN: | FileCheck %s -check-prefix=MIR
16 # MIR: renamable $w0 = LDRWui killed renamable $x8
17 # MIR-NEXT: DBG_VALUE $x0, 0, {{.*}}, !DIExpression(DW_OP_LLVM_entry_value, 1)
18 # MIR-NEXT: BL @baz
19 # MIR-NEXT: frame-destroy LDPXpost
20 # MIR-NEXT: TCRETURNdi @baz
/external/llvm-project/llvm/unittests/MI/
DLiveIntervalTest.cpp53 legacy::PassManagerBase &PM, std::unique_ptr<MIRParser> &MIR, in parseMIR() argument
57 MIR = createMIRParser(std::move(MBuffer), Context); in parseMIR()
58 if (!MIR) in parseMIR()
61 std::unique_ptr<Module> M = MIR->parseIRModule(); in parseMIR()
68 if (MIR->parseMachineFunctions(*M, MMIWP->getMMI())) in parseMIR()
171 std::unique_ptr<MIRParser> MIR; in liveIntervalTest() local
172 std::unique_ptr<Module> M = parseMIR(Context, PM, MIR, *TM, MIRString, in liveIntervalTest()
/external/llvm-project/llvm/docs/GlobalISel/
DPipeline.rst22 Converts :doc:`LLVM-IR <../LangRef>` into :doc:`gMIR (Generic MIR) <GMIR>`.
24 It's somewhat analogous to SelectionDAGBuilder but builds a flavour of MIR
26 same data structures as MIR but has more relaxed constraints. For example,
35 can shape the MIR as they wish.
40 cross-register-bank copies by clustering portions of the MIR together.
45 constrained enough that it becomes MIR.
56 The representation must be gMIR, MIR, or a mixture of the two after this pass.
58 gradually transition the gMIR to MIR.
71 have completed the conversion from gMIR to MIR.
135 and perform a single step of the algorithm and check the result. The MIR and
DPorting.rst15 * :ref:`InstructionSelector <api-instructionselector>` --- select generic MIR
16 to target-specific MIR.
/external/llvm/tools/llc/
Dllc.cpp274 std::unique_ptr<MIRParser> MIR; in compileModule() local
283 MIR = createMIRParserFromFile(InputFilename, Err, Context); in compileModule()
284 if (MIR) in compileModule()
285 M = MIR->parseLLVMModule(); in compileModule()
410 if (!MIR) { in compileModule()
418 LLVMTM.addMachineFunctionAnalysis(PM, MIR.get()); in compileModule()
465 MIR.get())) { in compileModule()
/external/llvm/test/CodeGen/MIR/Generic/
Dfunction-missing-machine-function.mir2 # This test verifies that an error is reported when a MIR file has some
5 # CHECK: no machine function information for function 'foo' in the MIR file
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.ds.gws.barrier.ll8 …er=postrapseudos -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=MIR %s
9 …er=postrapseudos -o - -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=MIR %s
28 ; MIR-LABEL: name: gws_barrier_offset0{{$}}
29 ; MIR: BUNDLE implicit{{( killed)?( renamable)?}} $vgpr0, implicit $m0, implicit $exec {
30 ; MIR-NEXT: DS_GWS_BARRIER renamable $vgpr0, 0, implicit $m0, implicit $exec :: (load 4 from custom…
31 ; MIR-NEXT: S_WAITCNT 0
32 ; MIR-NEXT: }
38 ; MIR-LABEL: name: gws_barrier_offset63{{$}}
/external/llvm-project/llvm/test/CodeGen/MIR/AArch64/
Dmultiple-lhs-operands.mir2 # This test ensures that the MIR parser can parse multiple register machine
5 # This tests that a MIR file with no vregs does not get altered by mir-canon.
/external/llvm-project/llvm/test/Verifier/
Ddiexpression-entry-value-llvm-ir.ll3 ; The DW_OP_LLVM_entry_value operation can only be used in MIR.
5 ; CHECK: Entry values are only allowed in MIR
/external/llvm-project/llvm/tools/llc/
Dllc.cpp404 std::unique_ptr<MIRParser> MIR; in compileModule() local
485 MIR = createMIRParserFromFile(InputFilename, Err, Context, in compileModule()
487 if (MIR) in compileModule()
488 M = MIR->parseIRModule(SetDataLayout); in compileModule()
602 if (!MIR) { in compileModule()
637 if (MIR) { in compileModule()
639 if (MIR->parseMachineFunctions(*M, MMIWP->getMMI())) in compileModule()

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