| /external/llvm-project/llvm/test/CodeGen/PowerPC/ |
| D | atomic-minmax.ll | 235 ; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 27
238 ; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 16
262 ; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 27
265 ; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 16
289 ; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 27
292 ; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 16
314 ; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 27
317 ; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 16
339 ; CHECK-DAG: rlwinm [[SA1:[0-9]+]], 3, 3, 27, 28
342 ; CHECK-DAG: xori [[SA:[0-9]+]], [[SA1]], 24
[all …]
|
| /external/skia/resources/sksl/shared/ |
| D | StructMaxDepth.sksl | 11 struct SA1 { int x[8]; };
12 struct SA2 { SA1 x[7]; };
|
| /external/skia/tests/sksl/shared/ |
| D | StructMaxDepth.glsl | 27 struct SA1 {
31 SA1 x[7];
|
| D | StructMaxDepth.metal | 28 struct SA1 {
32 array<SA1, 7> x;
|
| /external/rust/crates/libm/src/math/ |
| D | erf.rs | 149 const SA1: f64 = 1.96512716674392571292e+01; /* 0x4033A6B9, 0xBD707687 */ constant
204 + s * (SA1 in erfc2()
|
| D | erff.rs | 60 const SA1: f32 = 1.9651271820e+01; /* 0x419d35ce */ constant
114 + s * (SA1 in erfc2()
|
| /external/llvm/test/CodeGen/X86/ |
| D | mmx-coalescing.ll | 23 %SA1 = getelementptr inbounds %SA, %SA* %pSA, i64 0, i32 3
24 %v2 = load i8*, i8** %SA1, align 8
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.td | 143 def SA1 : Rc<2, "sa1", ["c2"]>, DwarfRegNum<[69]>;
168 def C3_2 : Rcc<2, "c3:2", [SA1, LC1], ["lc1:sa1"]>, DwarfRegNum<[69]>;
259 (add LC0, SA0, LC1, SA1,
273 LC0, LC1, SA0, SA1, USR, USR_OVF, CS0, CS1,
|
| D | HexagonRegisterInfo.cpp | 148 Reserved.set(Hexagon::SA1); in getReservedRegs()
|
| /external/llvm-project/clang/test/OpenMP/ |
| D | target_map_messages.cpp | 642 struct SA1{ struct
644 struct SA1 *p; argument
649 struct SA1 s; argument
650 struct SA1 sa[10];
651 struct SA1 *sp[10];
652 struct SA1 *p;
|
| /external/llvm-project/llvm/test/CodeGen/X86/ |
| D | mmx-coalescing.ll | 41 %SA1 = getelementptr inbounds %SA, %SA* %pSA, i64 0, i32 3
42 %v2 = load i8*, i8** %SA1, align 8
|
| /external/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCChecker.h | 111 return (Hexagon::SA0 == R || Hexagon::LC0 == R || Hexagon::SA1 == R || in isLoopRegister()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCChecker.h | 106 return (Hexagon::SA0 == R || Hexagon::LC0 == R || Hexagon::SA1 == R || in isLoopRegister()
|
| /external/ipsec-tools/src/racoon/ |
| D | TODO | 50 +--------------SA1----------------+
64 +--------------SA1----------------+
|
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCChecker.h | 189 Hexagon::SA1 == R || Hexagon::LC1 == R); in isLoopRegister()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| D | HexagonRegisterInfo.td | 136 def SA1: Rc<2, "sa1", ["c2"]>, DwarfRegNum<[69]>;
168 def C3_2 : Rcc<2, "c3:2", [SA1, LC1], ["lc1:sa1"]>, DwarfRegNum<[69]>;
363 (add LC0, SA0, LC1, SA1, P3_0, C5, C8, PC, UGP, GP, CS0, CS1,
|
| D | HexagonPseudo.td | 98 Defs = [PC, LC1], Uses = [SA1, LC1] in {
105 Defs = [PC, LC0, LC1], Uses = [SA0, SA1, LC0, LC1] in {
156 let Defs = [SA1, LC1], isCodeGenOnly = 1, isExtended = 1, opExtendable = 0 in {
|
| D | HexagonRegisterInfo.cpp | 152 Reserved.set(Hexagon::SA1); // C2 in getReservedRegs()
|
| /external/llvm-project/llvm/lib/Target/Hexagon/ |
| D | HexagonPseudo.td | 98 Defs = [PC, LC1], Uses = [SA1, LC1] in {
105 Defs = [PC, LC0, LC1], Uses = [SA0, SA1, LC0, LC1] in {
156 let Defs = [SA1, LC1], isCodeGenOnly = 1, isExtended = 1, opExtendable = 0 in {
|
| D | HexagonRegisterInfo.td | 150 def SA1: Rc<2, "sa1", ["c2"]>, DwarfRegNum<[69]>;
182 def C3_2 : Rcc<2, "c3:2", [SA1, LC1], ["lc1:sa1"]>, DwarfRegNum<[69]>;
399 (add LC0, SA0, LC1, SA1, P3_0, C5, C8, PC, UGP, GP, CS0, CS1,
|
| D | HexagonRegisterInfo.cpp | 152 Reserved.set(Hexagon::SA1); // C2 in getReservedRegs()
|
| /external/angle/src/libANGLE/renderer/vulkan/doc/ |
| D | PresentSemaphores.md | 98 …S:SA1 | W:SA1 | | S:SA2 | W:SA2 | | S:SA3 | | W:SA3 | | S:SA4 | | W:SA…
|
| /external/llvm-project/llvm/unittests/Analysis/ |
| D | MemorySSATest.cpp | 1055 StoreInst *SA1 = B.CreateStore(ConstantInt::get(Int8, 1), AllocaA); in TEST_F() local
1067 for (StoreInst *V : {SA1, SB1, SA2, SB2, SA3, SB3}) { in TEST_F()
1074 if (V == SA1) in TEST_F()
1151 StoreInst *SA1 = B.CreateStore(ConstantInt::get(Int8, 0), PointerA); in TEST_F() local
1164 std::initializer_list<StoreInst *> Sts = {SA1, SB1, SC1, SA2, SB2, SC2, SB3}; in TEST_F()
|
| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineSelect.cpp | 2283 Value *SA0, *SA1; in foldSelectRotate() local
2285 !match(Or1, m_OneUse(m_LogicalShift(m_Specific(TVal), m_Value(SA1))))) in foldSelectRotate()
2303 if (match(SA1, m_OneUse(m_Sub(m_SpecificInt(Width), m_Specific(SA0))))) in foldSelectRotate()
2305 else if (match(SA0, m_OneUse(m_Sub(m_SpecificInt(Width), m_Specific(SA1))))) in foldSelectRotate()
2306 ShAmt = SA1; in foldSelectRotate()
2320 (ShAmt == SA1 && ShiftOpcode1 == BinaryOperator::Shl); in foldSelectRotate()
|
| /external/llvm-project/llvm/lib/Transforms/InstCombine/ |
| D | InstCombineSelect.cpp | 2336 Value *SV0, *SV1, *SA0, *SA1; in foldSelectFunnelShift() local
2340 m_ZExtOrSelf(m_Value(SA1))))) || in foldSelectFunnelShift()
2348 std::swap(SA0, SA1); in foldSelectFunnelShift()
2356 if (match(SA1, m_OneUse(m_Sub(m_SpecificInt(Width), m_Specific(SA0))))) in foldSelectFunnelShift()
2358 else if (match(SA0, m_OneUse(m_Sub(m_SpecificInt(Width), m_Specific(SA1))))) in foldSelectFunnelShift()
2359 ShAmt = SA1; in foldSelectFunnelShift()
|