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Searched refs:Sched (Results 1 – 25 of 203) sorted by relevance

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/external/llvm-project/llvm/lib/Target/Hexagon/
DHexagonDepTimingClasses.h21 case Hexagon::Sched::tc_112d30d6: in is_TC1()
22 case Hexagon::Sched::tc_151bf368: in is_TC1()
23 case Hexagon::Sched::tc_1c2c7a4a: in is_TC1()
24 case Hexagon::Sched::tc_1d41f8b7: in is_TC1()
25 case Hexagon::Sched::tc_23708a21: in is_TC1()
26 case Hexagon::Sched::tc_24f426ab: in is_TC1()
27 case Hexagon::Sched::tc_2f573607: in is_TC1()
28 case Hexagon::Sched::tc_388f9897: in is_TC1()
29 case Hexagon::Sched::tc_3d14a17b: in is_TC1()
30 case Hexagon::Sched::tc_3fbf1042: in is_TC1()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
DHexagonDepTimingClasses.h21 case Hexagon::Sched::tc_05d3a09b: in is_TC3x()
22 case Hexagon::Sched::tc_0d8f5752: in is_TC3x()
23 case Hexagon::Sched::tc_13bfbcf9: in is_TC3x()
24 case Hexagon::Sched::tc_174516e8: in is_TC3x()
25 case Hexagon::Sched::tc_1a2fd869: in is_TC3x()
26 case Hexagon::Sched::tc_1c4528a2: in is_TC3x()
27 case Hexagon::Sched::tc_32779c6f: in is_TC3x()
28 case Hexagon::Sched::tc_5b54b33f: in is_TC3x()
29 case Hexagon::Sched::tc_6b25e783: in is_TC3x()
30 case Hexagon::Sched::tc_76851da1: in is_TC3x()
[all …]
/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVInstrInfoB.td202 def ANDN : ALU_rr<0b0100000, 0b111, "andn">, Sched<[]>;
203 def ORN : ALU_rr<0b0100000, 0b110, "orn">, Sched<[]>;
204 def XNOR : ALU_rr<0b0100000, 0b100, "xnor">, Sched<[]>;
208 def SLO : ALU_rr<0b0010000, 0b001, "slo">, Sched<[]>;
209 def SRO : ALU_rr<0b0010000, 0b101, "sro">, Sched<[]>;
213 def ROL : ALU_rr<0b0110000, 0b001, "rol">, Sched<[]>;
214 def ROR : ALU_rr<0b0110000, 0b101, "ror">, Sched<[]>;
218 def SBCLR : ALU_rr<0b0100100, 0b001, "sbclr">, Sched<[]>;
219 def SBSET : ALU_rr<0b0010100, 0b001, "sbset">, Sched<[]>;
220 def SBINV : ALU_rr<0b0110100, 0b001, "sbinv">, Sched<[]>;
[all …]
DRISCVInstrInfoM.td28 Sched<[WriteIMul, ReadIMul, ReadIMul]>;
30 Sched<[WriteIMul, ReadIMul, ReadIMul]>;
32 Sched<[WriteIMul, ReadIMul, ReadIMul]>;
34 Sched<[WriteIMul, ReadIMul, ReadIMul]>;
36 Sched<[WriteIDiv, ReadIDiv, ReadIDiv]>;
38 Sched<[WriteIDiv, ReadIDiv, ReadIDiv]>;
40 Sched<[WriteIDiv, ReadIDiv, ReadIDiv]>;
42 Sched<[WriteIDiv, ReadIDiv, ReadIDiv]>;
47 Sched<[WriteIMul32, ReadIMul32, ReadIMul32]>;
49 Sched<[WriteIDiv32, ReadIDiv32, ReadIDiv32]>;
[all …]
DRISCVInstrInfoZfh.td63 Sched<[]>;
74 Sched<[]>;
83 Sched<[]>;
86 Sched<[]>;
89 Sched<[]>;
92 Sched<[]>;
95 Sched<[]>;
99 Sched<[]>;
102 Sched<[]>;
105 Sched<[]>;
[all …]
DRISCVInstrInfoD.td61 Sched<[WriteFCmp64, ReadFCmp64, ReadFCmp64]>;
73 Sched<[WriteFLD64, ReadFMemBase]>;
82 Sched<[WriteFST64, ReadStoreData, ReadFMemBase]>;
85 Sched<[WriteFMulAdd64, ReadFMulAdd64, ReadFMulAdd64, ReadFMulAdd64]>;
88 Sched<[WriteFMulSub64, ReadFMulSub64, ReadFMulSub64, ReadFMulSub64]>;
91 Sched<[WriteFMulSub64, ReadFMulSub64, ReadFMulSub64, ReadFMulSub64]>;
94 Sched<[WriteFMulAdd64, ReadFMulAdd64, ReadFMulAdd64, ReadFMulAdd64]>;
98 Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>;
101 Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>;
104 Sched<[WriteFMul64, ReadFMul64, ReadFMul64]>;
[all …]
DRISCVInstrInfoC.td290 Sched<[WriteIALU, ReadIALU]> {
300 Sched<[WriteFLD64, ReadMemBase]> {
307 Sched<[WriteLDW, ReadMemBase]> {
317 Sched<[WriteFLD32, ReadMemBase]> {
326 Sched<[WriteLDD, ReadMemBase]> {
334 Sched<[WriteFST64, ReadStoreData, ReadMemBase]> {
341 Sched<[WriteSTW, ReadStoreData, ReadMemBase]> {
351 Sched<[WriteFST32, ReadStoreData, ReadMemBase]> {
360 Sched<[WriteSTD, ReadStoreData, ReadMemBase]> {
368 Sched<[WriteNop]>
[all …]
DRISCVInstrInfoF.td97 Sched<[WriteFCmp32, ReadFCmp32, ReadFCmp32]>;
108 Sched<[WriteFLD32, ReadFMemBase]>;
117 Sched<[WriteFST32, ReadStoreData, ReadFMemBase]>;
120 Sched<[WriteFMulAdd32, ReadFMulAdd32, ReadFMulAdd32, ReadFMulAdd32]>;
123 Sched<[WriteFMulSub32, ReadFMulSub32, ReadFMulSub32, ReadFMulSub32]>;
126 Sched<[WriteFMulSub32, ReadFMulSub32, ReadFMulSub32, ReadFMulSub32]>;
129 Sched<[WriteFMulAdd32, ReadFMulAdd32, ReadFMulAdd32, ReadFMulAdd32]>;
133 Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>;
136 Sched<[WriteFALU32, ReadFALU32, ReadFALU32]>;
139 Sched<[WriteFMul32, ReadFMul32, ReadFMul32]>;
[all …]
DRISCVInstrInfoA.td80 defm LR_W : LR_r_aq_rl<0b010, "lr.w">, Sched<[WriteAtomicLDW, ReadAtomicLDW]>;
82 Sched<[WriteAtomicSTW, ReadAtomicSTW, ReadAtomicSTW]>;
84 Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
86 Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
88 Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
90 Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
92 Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
94 Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
96 Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
98 Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
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/external/llvm/lib/Target/PowerPC/
DPPCHazardRecognizers.cpp68 if (!PredMCID || PredMCID->getSchedClass() != PPC::Sched::IIC_SprMTSPR) in isBCTRAfterSet()
97 case PPC::Sched::IIC_IntDivW: in mustComeFirst()
98 case PPC::Sched::IIC_IntDivD: in mustComeFirst()
99 case PPC::Sched::IIC_LdStLoadUpd: in mustComeFirst()
100 case PPC::Sched::IIC_LdStLDU: in mustComeFirst()
101 case PPC::Sched::IIC_LdStLFDU: in mustComeFirst()
102 case PPC::Sched::IIC_LdStLFDUX: in mustComeFirst()
103 case PPC::Sched::IIC_LdStLHA: in mustComeFirst()
104 case PPC::Sched::IIC_LdStLHAU: in mustComeFirst()
105 case PPC::Sched::IIC_LdStLWA: in mustComeFirst()
[all …]
/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCHazardRecognizers.cpp66 if (!PredMCID || PredMCID->getSchedClass() != PPC::Sched::IIC_SprMTSPR) in isBCTRAfterSet()
95 case PPC::Sched::IIC_IntDivW: in mustComeFirst()
96 case PPC::Sched::IIC_IntDivD: in mustComeFirst()
97 case PPC::Sched::IIC_LdStLoadUpd: in mustComeFirst()
98 case PPC::Sched::IIC_LdStLDU: in mustComeFirst()
99 case PPC::Sched::IIC_LdStLFDU: in mustComeFirst()
100 case PPC::Sched::IIC_LdStLFDUX: in mustComeFirst()
101 case PPC::Sched::IIC_LdStLHA: in mustComeFirst()
102 case PPC::Sched::IIC_LdStLHAU: in mustComeFirst()
103 case PPC::Sched::IIC_LdStLWA: in mustComeFirst()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCHazardRecognizers.cpp66 if (!PredMCID || PredMCID->getSchedClass() != PPC::Sched::IIC_SprMTSPR) in isBCTRAfterSet()
95 case PPC::Sched::IIC_IntDivW: in mustComeFirst()
96 case PPC::Sched::IIC_IntDivD: in mustComeFirst()
97 case PPC::Sched::IIC_LdStLoadUpd: in mustComeFirst()
98 case PPC::Sched::IIC_LdStLDU: in mustComeFirst()
99 case PPC::Sched::IIC_LdStLFDU: in mustComeFirst()
100 case PPC::Sched::IIC_LdStLFDUX: in mustComeFirst()
101 case PPC::Sched::IIC_LdStLHA: in mustComeFirst()
102 case PPC::Sched::IIC_LdStLHAU: in mustComeFirst()
103 case PPC::Sched::IIC_LdStLWA: in mustComeFirst()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrExtension.td16 "{cbtw|cbw}", []>, OpSize16, Sched<[WriteALU]>;
19 "{cwtl|cwde}", []>, OpSize32, Sched<[WriteALU]>;
22 "{cltq|cdqe}", []>, Sched<[WriteALU]>, Requires<[In64BitMode]>;
28 "{cwtd|cwd}", []>, OpSize16, Sched<[WriteALU]>;
31 "{cltd|cdq}", []>, OpSize32, Sched<[WriteALU]>;
34 "{cqto|cqo}", []>, Sched<[WriteALU]>, Requires<[In64BitMode]>;
41 TB, OpSize16, Sched<[WriteALU]>;
45 TB, OpSize16, Sched<[WriteALULd]>;
50 OpSize32, Sched<[WriteALU]>;
54 OpSize32, Sched<[WriteALULd]>;
[all …]
DX86InstrControl.td129 OpSize16, Sched<[WriteJump]>;
132 OpSize16, Sched<[WriteJumpLd]>;
136 OpSize32, Sched<[WriteJump]>;
139 OpSize32, Sched<[WriteJumpLd]>;
143 Sched<[WriteJump]>;
146 Sched<[WriteJumpLd]>;
152 "rex64 jmp{q}\t{*}$dst", []>, Sched<[WriteJump]>;
155 "rex64 jmp{q}\t{*}$dst", []>, Sched<[WriteJumpLd]>;
163 OpSize16, Sched<[WriteJump]>, NOTRACK;
167 Requires<[Not64BitMode]>, OpSize16, Sched<[WriteJumpLd]>,
[all …]
/external/llvm-project/llvm/lib/Target/X86/
DX86InstrExtension.td16 "{cbtw|cbw}", []>, OpSize16, Sched<[WriteALU]>;
19 "{cwtl|cwde}", []>, OpSize32, Sched<[WriteALU]>;
22 "{cltq|cdqe}", []>, Sched<[WriteALU]>, Requires<[In64BitMode]>;
28 "{cwtd|cwd}", []>, OpSize16, Sched<[WriteALU]>;
31 "{cltd|cdq}", []>, OpSize32, Sched<[WriteALU]>;
34 "{cqto|cqo}", []>, Sched<[WriteALU]>, Requires<[In64BitMode]>;
41 TB, OpSize16, Sched<[WriteALU]>;
45 TB, OpSize16, Sched<[WriteALULd]>;
50 OpSize32, Sched<[WriteALU]>;
54 OpSize32, Sched<[WriteALULd]>;
[all …]
DX86InstrControl.td129 OpSize16, Sched<[WriteJump]>;
132 OpSize16, Sched<[WriteJumpLd]>;
136 OpSize32, Sched<[WriteJump]>;
139 OpSize32, Sched<[WriteJumpLd]>;
143 Sched<[WriteJump]>;
146 Sched<[WriteJumpLd]>;
152 "rex64 jmp{q}\t{*}$dst", []>, Sched<[WriteJump]>;
155 "rex64 jmp{q}\t{*}$dst", []>, Sched<[WriteJumpLd]>;
163 OpSize16, Sched<[WriteJump]>, NOTRACK;
167 Requires<[Not64BitMode]>, OpSize16, Sched<[WriteJumpLd]>,
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVInstrInfoM.td28 Sched<[WriteIMul, ReadIMul, ReadIMul]>;
30 Sched<[WriteIMul, ReadIMul, ReadIMul]>;
32 Sched<[WriteIMul, ReadIMul, ReadIMul]>;
34 Sched<[WriteIMul, ReadIMul, ReadIMul]>;
36 Sched<[WriteIDiv, ReadIDiv, ReadIDiv]>;
38 Sched<[WriteIDiv, ReadIDiv, ReadIDiv]>;
40 Sched<[WriteIDiv, ReadIDiv, ReadIDiv]>;
42 Sched<[WriteIDiv, ReadIDiv, ReadIDiv]>;
47 Sched<[WriteIMul32, ReadIMul32, ReadIMul32]>;
49 Sched<[WriteIDiv32, ReadIDiv32, ReadIDiv32]>;
[all …]
DRISCVInstrInfoC.td286 Sched<[WriteIALU, ReadIALU]> {
296 Sched<[WriteFLD64, ReadMemBase]> {
303 Sched<[WriteLDW, ReadMemBase]> {
313 Sched<[WriteFLD32, ReadMemBase]> {
322 Sched<[WriteLDD, ReadMemBase]> {
330 Sched<[WriteFST64, ReadStoreData, ReadMemBase]> {
337 Sched<[WriteSTW, ReadStoreData, ReadMemBase]> {
347 Sched<[WriteFST32, ReadStoreData, ReadMemBase]> {
356 Sched<[WriteSTD, ReadStoreData, ReadMemBase]> {
364 Sched<[WriteNop]>
[all …]
DRISCVInstrInfoD.td46 Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>;
53 Sched<[WriteFALU64, ReadFALU64, ReadFALU64]>;
63 Sched<[WriteFCmp64, ReadFCmp64, ReadFCmp64]>;
75 Sched<[WriteFLD64, ReadMemBase]>;
84 Sched<[WriteFST64, ReadStoreData, ReadMemBase]>;
87 Sched<[WriteFMulAdd64, ReadFMulAdd64, ReadFMulAdd64, ReadFMulAdd64]>;
90 Sched<[WriteFMulSub64, ReadFMulSub64, ReadFMulSub64, ReadFMulSub64]>;
93 Sched<[WriteFMulSub64, ReadFMulSub64, ReadFMulSub64, ReadFMulSub64]>;
96 Sched<[WriteFMulAdd64, ReadFMulAdd64, ReadFMulAdd64, ReadFMulAdd64]>;
109 Sched<[WriteFSqrt32, ReadFSqrt32]> {
[all …]
DRISCVInstrInfoA.td80 defm LR_W : LR_r_aq_rl<0b010, "lr.w">, Sched<[WriteAtomicLDW, ReadAtomicLDW]>;
82 Sched<[WriteAtomicSTW, ReadAtomicSTW, ReadAtomicSTW]>;
84 Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
86 Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
88 Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
90 Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
92 Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
94 Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
96 Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
98 Sched<[WriteAtomicW, ReadAtomicWA, ReadAtomicWD]>;
[all …]
/external/llvm/lib/Target/X86/
DX86InstrExtension.td45 TB, OpSize16, Sched<[WriteALU]>;
49 TB, OpSize16, Sched<[WriteALULd]>;
54 OpSize32, Sched<[WriteALU]>;
58 OpSize32, Sched<[WriteALULd]>;
62 OpSize32, Sched<[WriteALU]>;
66 OpSize32, TB, Sched<[WriteALULd]>;
71 TB, OpSize16, Sched<[WriteALU]>;
75 TB, OpSize16, Sched<[WriteALULd]>;
80 OpSize32, Sched<[WriteALU]>;
84 OpSize32, Sched<[WriteALULd]>;
[all …]
DX86InstrMMX.td23 let Sched = WriteVecALU in {
41 let Sched = WriteVecLogic in
46 let Sched = WriteVecIMul in
51 let Sched = WriteVecIMul in {
65 let Sched = WriteShuffle in {
81 } // Sched
83 let Sched = WriteCvtF2I in {
102 Sched<[itins.Sched]> {
110 itins.rm>, Sched<[itins.Sched.Folded, ReadAfterLd]>;
120 Sched<[WriteVecShift]>;
[all …]
DX86InstrControl.td137 OpSize16, Sched<[WriteJump]>;
140 Requires<[Not64BitMode]>, OpSize16, Sched<[WriteJumpLd]>;
144 OpSize32, Sched<[WriteJump]>;
147 Requires<[Not64BitMode]>, OpSize32, Sched<[WriteJumpLd]>;
151 Sched<[WriteJump]>;
154 Requires<[In64BitMode]>, Sched<[WriteJumpLd]>;
160 IIC_JMP_FAR_PTR>, OpSize16, Sched<[WriteJump]>;
164 IIC_JMP_FAR_PTR>, OpSize32, Sched<[WriteJump]>;
168 Sched<[WriteJump]>;
172 Sched<[WriteJumpLd]>;
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DARMInstrThumb.td392 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
405 T1Encoding<{1,0,1,0,1,?}>, Sched<[WriteALU]> {
425 T1Misc<{0,0,0,0,0,?,?}>, Sched<[WriteALU]> {
436 T1Misc<{0,0,0,0,1,?,?}>, Sched<[WriteALU]> {
457 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
469 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
485 T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
494 T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
504 [(ARMretflag)], (tBX LR, pred:$p)>, Sched<[WriteBr]>;
508 [(ARMseretflag)]>, Sched<[WriteBr]>;
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMInstrThumb.td388 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
401 T1Encoding<{1,0,1,0,1,?}>, Sched<[WriteALU]> {
421 T1Misc<{0,0,0,0,0,?,?}>, Sched<[WriteALU]> {
432 T1Misc<{0,0,0,0,1,?,?}>, Sched<[WriteALU]> {
453 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
465 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
481 T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
490 T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
500 [(ARMretflag)], (tBX LR, pred:$p)>, Sched<[WriteBr]>;
505 (tBX GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;
[all …]

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