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Searched refs:rad_info (Results 1 – 21 of 21) sorted by relevance

/external/mesa3d/src/amd/vulkan/
Dradv_rgp.c333 struct radeon_info *rad_info = &device->physical_device->rad_info; in radv_fill_sqtt_asic_info() local
334 bool has_wave32 = rad_info->chip_class >= GFX10; in radv_fill_sqtt_asic_info()
347 if (rad_info->chip_class < GFX9) in radv_fill_sqtt_asic_info()
351 if (rad_info->family == CHIP_FIJI || rad_info->chip_class >= GFX9) in radv_fill_sqtt_asic_info()
354 chunk->trace_shader_core_clock = rad_info->max_shader_clock * 1000000; in radv_fill_sqtt_asic_info()
355 chunk->trace_memory_clock = rad_info->max_memory_clock * 1000000; in radv_fill_sqtt_asic_info()
357 chunk->device_id = rad_info->pci_id; in radv_fill_sqtt_asic_info()
358 chunk->device_revision_id = rad_info->pci_rev_id; in radv_fill_sqtt_asic_info()
359 chunk->vgprs_per_simd = rad_info->num_physical_wave64_vgprs_per_simd * in radv_fill_sqtt_asic_info()
361 chunk->sgprs_per_simd = rad_info->num_physical_sgprs_per_simd; in radv_fill_sqtt_asic_info()
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Dsi_cmd_buffer.c42 unsigned num_se = MAX2(physical_device->rad_info.max_se, 1); in si_write_harvested_raster_configs()
46 ac_get_harvested_configs(&physical_device->rad_info, in si_write_harvested_raster_configs()
53 if (physical_device->rad_info.chip_class < GFX7) in si_write_harvested_raster_configs()
66 if (physical_device->rad_info.chip_class < GFX7) in si_write_harvested_raster_configs()
76 if (physical_device->rad_info.chip_class >= GFX7) in si_write_harvested_raster_configs()
95 if (device->physical_device->rad_info.chip_class >= GFX7) { in si_emit_compute()
113 if (device->physical_device->rad_info.chip_class >= GFX9) { in si_emit_compute()
115 device->physical_device->rad_info.chip_class >= GFX10 ? 0x20 : 0); in si_emit_compute()
118 if (device->physical_device->rad_info.chip_class >= GFX10) { in si_emit_compute()
132 if (device->physical_device->rad_info.chip_class <= GFX6) { in si_emit_compute()
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Dradv_sqtt.c70 unsigned max_se = device->physical_device->rad_info.max_se; in radv_emit_thread_trace_start()
72 assert(device->physical_device->rad_info.chip_class >= GFX8); in radv_emit_thread_trace_start()
84 if (device->physical_device->rad_info.chip_class == GFX10) { in radv_emit_thread_trace_start()
142 if (device->physical_device->rad_info.chip_class < GFX9) { in radv_emit_thread_trace_start()
166 if (device->physical_device->rad_info.chip_class == GFX9) { in radv_emit_thread_trace_start()
183 if (device->physical_device->rad_info.chip_class == GFX9) { in radv_emit_thread_trace_start()
201 device->physical_device->rad_info.chip_class >= GFX7) { in radv_emit_thread_trace_start()
238 switch (device->physical_device->rad_info.chip_class) { in radv_copy_thread_trace_info_regs()
273 unsigned max_se = device->physical_device->rad_info.max_se; in radv_emit_thread_trace_stop()
275 assert(device->physical_device->rad_info.chip_class >= GFX8); in radv_emit_thread_trace_stop()
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Dradv_shader.c449 .float16 = device->physical_device->rad_info.has_packed_math_16bit, in radv_shader_compile_to_nir()
570 if (device->physical_device->rad_info.chip_class == GFX6) { in radv_shader_compile_to_nir()
622 bool gfx7minus = device->physical_device->rad_info.chip_class <= GFX7; in radv_shader_compile_to_nir()
683 if (ac_lower_indirect_derefs(nir, device->physical_device->rad_info.chip_class) && in radv_shader_compile_to_nir()
816 (device->physical_device->rad_info.cpdma_prefetch_writes_memory ? in radv_alloc_shader_memory()
884 assert((pdevice->rad_info.chip_class >= GFX10 && num_shared_vgprs % 8 == 0) in radv_postprocess_config()
885 || (pdevice->rad_info.chip_class < GFX10 && num_shared_vgprs == 0)); in radv_postprocess_config()
918 if (pdevice->rad_info.chip_class >= GFX10) { in radv_postprocess_config()
928 config_out->rsrc1 |= S_00B228_MEM_ORDERED(pdevice->rad_info.chip_class >= GFX10); in radv_postprocess_config()
932 assert(pdevice->rad_info.chip_class <= GFX8); in radv_postprocess_config()
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Dradv_debug.c79 ac_vm_fault_occured(device->physical_device->rad_info.chip_class, in radv_init_trace()
99 ac_dump_reg(f, device->physical_device->rad_info.chip_class, in radv_dump_mmapped_reg()
106 struct radeon_info *info = &device->physical_device->rad_info; in radv_dump_debug_registers()
193 enum chip_class chip_class = device->physical_device->rad_info.chip_class; in radv_dump_descriptor_set()
374 enum chip_class chip_class = pipeline->device->physical_device->rad_info.chip_class; in radv_dump_annotated_shaders()
534 struct radeon_info *info = &device->physical_device->rad_info; in radv_dump_device_name()
563 device->physical_device->rad_info.chip_class >= GFX10 ? "gfx_0.0.0" : "gfx"); in radv_dump_umr_ring()
581 device->physical_device->rad_info.chip_class >= GFX10 ? "gfx_0.0.0" : "gfx"); in radv_dump_umr_waves()
612 vm_fault_occurred = ac_vm_fault_occured(device->physical_device->rad_info.chip_class, in radv_check_gpu_hangs()
694 ac_print_gpu_info(&device->physical_device->rad_info, f); in radv_check_gpu_hangs()
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Dradv_device.c148 return MIN2(device->rad_info.vram_size, (uint64_t)ov << 20); in radv_get_adjusted_vram_size()
149 return device->rad_info.vram_size; in radv_get_adjusted_vram_size()
155 return MIN2(radv_get_adjusted_vram_size(device) , device->rad_info.vram_vis_size); in radv_get_visible_vram_size()
161 return radv_get_adjusted_vram_size(device) - device->rad_info.vram_vis_size; in radv_get_vram_size()
191 if (device->rad_info.gart_size > 0) { in radv_physical_device_init_mem_types()
195 .size = device->rad_info.gart_size, in radv_physical_device_init_mem_types()
252 if (device->rad_info.has_l2_uncached) { in radv_physical_device_init_mem_types()
385 device->ws->query_info(device->ws, &device->rad_info); in radv_physical_device_try_create()
391 device->rad_info.name, radv_get_compiler_string(device)); in radv_physical_device_try_create()
393 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) { in radv_physical_device_try_create()
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Dradv_pipeline.c248 4 * device->physical_device->rad_info.num_good_compute_units * in radv_pipeline_init_scratch()
795 if (pipeline->device->physical_device->rad_info.has_rbplus) { in radv_pipeline_init_blend_state()
1092 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes; in radv_pipeline_init_multisample_state()
1168 …_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX… in radv_pipeline_init_multisample_state()
1203 …S_028BE0_COVERED_CENTROID_IS_CENTER(pipeline->device->physical_device->rad_info.chip_class >= GFX1… in radv_pipeline_init_multisample_state()
1400 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8) in radv_compute_ia_multi_vgt_param_helpers()
1420 if ((device->physical_device->rad_info.family == CHIP_TAHITI || in radv_compute_ia_multi_vgt_param_helpers()
1421 device->physical_device->rad_info.family == CHIP_PITCAIRN || in radv_compute_ia_multi_vgt_param_helpers()
1422 device->physical_device->rad_info.family == CHIP_BONAIRE) && in radv_compute_ia_multi_vgt_param_helpers()
1426 if (device->physical_device->rad_info.has_distributed_tess) { in radv_compute_ia_multi_vgt_param_helpers()
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Dradv_image.c52 && device->physical_device->rad_info.chip_class <= GFX8) { in radv_choose_tiling()
75 if (device->physical_device->rad_info.chip_class < GFX8) in radv_use_tc_compat_htile_for_image()
101 device->physical_device->rad_info.chip_class >= GFX10))) in radv_use_tc_compat_htile_for_image()
143 if (device->physical_device->rad_info.chip_class >= GFX9) in radv_surface_has_scanout()
183 if (device->physical_device->rad_info.chip_class < GFX8) in radv_use_dcc_for_image()
208 device->physical_device->rad_info.chip_class >= GFX9) in radv_use_dcc_for_image()
284 if (device->physical_device->rad_info.chip_class < GFX8) in radv_use_tc_compat_cmask_for_image()
301 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id; in si_get_bo_metadata_word1()
325 if (device->physical_device->rad_info.chip_class >= GFX9) { in radv_patch_surface_from_metadata()
370 if (device->physical_device->rad_info.chip_class >= GFX10) { in radv_patch_image_dimensions()
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Dradv_cs.h122 if (pdevice->rad_info.chip_class < GFX10) in radeon_set_sh_reg_idx()
165 if (pdevice->rad_info.chip_class < GFX9 || in radeon_set_uconfig_reg_idx()
166 (pdevice->rad_info.chip_class == GFX9 && pdevice->rad_info.me_fw_version < 26)) in radeon_set_uconfig_reg_idx()
Dradv_cmd_buffer.c323 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7; in radv_cmd_buffer_uses_mec()
441 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 && in radv_reset_cmd_buffer()
443 unsigned num_db = cmd_buffer->device->physical_device->rad_info.num_render_backends; in radv_reset_cmd_buffer()
454 if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) { in radv_reset_cmd_buffer()
617 cmd_buffer->device->physical_device->rad_info.chip_class, in radv_cmd_buffer_after_draw()
975 if (pipeline->device->physical_device->rad_info.chip_class < GFX9) in radv_update_binning_state()
984 if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 || in radv_update_binning_state()
985 cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 || in radv_update_binning_state()
986 cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 || in radv_update_binning_state()
987 cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) { in radv_update_binning_state()
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Dradv_formats.c595 if (format == VK_FORMAT_E5B9G9R9_UFLOAT_PACK32 && pdevice->rad_info.chip_class < GFX10_3) in radv_is_colorbuffer_format_supported()
640 return physical_device->rad_info.family == CHIP_VEGA10 || in radv_device_supports_etc()
641 physical_device->rad_info.family == CHIP_RAVEN || in radv_device_supports_etc()
642 physical_device->rad_info.family == CHIP_RAVEN2 || in radv_device_supports_etc()
643 physical_device->rad_info.family == CHIP_STONEY; in radv_device_supports_etc()
787 if (physical_device->rad_info.chip_class <= GFX8 && in radv_physical_device_get_format_properties()
788 physical_device->rad_info.family != CHIP_STONEY) { in radv_physical_device_get_format_properties()
1150 enum chip_class chip_class = physical_device->rad_info.chip_class; in radv_get_image_format_properties()
1230 if (physical_device->rad_info.chip_class >= GFX9 && in radv_get_image_format_properties()
1494 if (physical_device->rad_info.chip_class >= GFX9) { in radv_GetPhysicalDeviceImageFormatProperties2()
Dradv_meta_bufimage.c138 if (device->physical_device->rad_info.chip_class >= GFX9) in radv_device_init_meta_itob_state()
214 if (device->physical_device->rad_info.chip_class >= GFX9) { in radv_device_init_meta_itob_state()
259 if (device->physical_device->rad_info.chip_class >= GFX9) in radv_device_finish_meta_itob_state()
364 if (device->physical_device->rad_info.chip_class >= GFX9) in radv_device_init_meta_btoi_state()
439 if (device->physical_device->rad_info.chip_class >= GFX9) { in radv_device_init_meta_btoi_state()
788 if (device->physical_device->rad_info.chip_class >= GFX9) in radv_device_init_meta_itoi_state()
863 if (device->physical_device->rad_info.chip_class >= GFX9) { in radv_device_init_meta_itoi_state()
907 if (device->physical_device->rad_info.chip_class >= GFX9) in radv_device_finish_meta_itoi_state()
1198 if (device->physical_device->rad_info.chip_class >= GFX9) in radv_device_init_meta_cleari_state()
1268 if (device->physical_device->rad_info.chip_class >= GFX9) { in radv_device_init_meta_cleari_state()
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Dradv_query.c168 unsigned enabled_rb_mask = device->physical_device->rad_info.enabled_rb_mask; in build_occlusion_query_shader()
169 unsigned db_count = device->physical_device->rad_info.num_render_backends; in build_occlusion_query_shader()
1171 pool->stride = 16 * device->physical_device->rad_info.num_render_backends; in radv_CreateQueryPool()
1277 uint32_t db_count = device->physical_device->rad_info.num_render_backends; in radv_GetQueryPoolResults()
1278 uint32_t enabled_rb_mask = device->physical_device->rad_info.enabled_rb_mask; in radv_GetQueryPoolResults()
1755 cmd_buffer->device->physical_device->rad_info.chip_class, in emit_end_query()
1803 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { in emit_end_query()
1922 cmd_buffer->device->physical_device->rad_info.chip_class, in radv_CmdWriteTimestamp()
1938 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { in radv_CmdWriteTimestamp()
Dradv_pipeline_cache.c475 if (header.device_id != device->physical_device->rad_info.pci_id) in radv_pipeline_cache_load()
588 header->device_id = device->physical_device->rad_info.pci_id; in radv_GetPipelineCacheData()
Dradv_meta_clear.c1037 device->physical_device->rad_info.family == CHIP_STONEY) in radv_image_can_fast_clear()
1478 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { in radv_clear_cmask()
1505 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { in radv_clear_fmask()
1536 if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) { in radv_clear_dcc()
1747 cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) { in radv_can_fast_clear_color()
Dradv_meta_blit2d.c61 …VkImageViewType view_type = cmd_buffer->device->physical_device->rad_info.chip_class < GFX9 ? VK_I… in create_iview()
417 bool use_3d = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 && in radv_meta_blit2d()
1376 bool create_3d = device->physical_device->rad_info.chip_class >= GFX9; in radv_device_init_meta_blit2d_state()
Dradv_meta_copy.c115 if (device->physical_device->rad_info.chip_class >= GFX9 && in image_is_renderable()
Dradv_private.h285 struct radeon_info rad_info; member
1602 (va >> 32) == device->physical_device->rad_info.address32_hi); in radv_emit_shader_pointer_body()
Dradv_descriptor_set.c923 if (device->physical_device->rad_info.chip_class >= GFX10) { in write_buffer_descriptor()
/external/wpa_supplicant_8/src/ap/
Dbeacon.c825 struct radius_sta rad_info; in handle_probe_req() local
839 &rad_info, 1); in handle_probe_req()
Dieee802_11.c3430 struct radius_sta rad_info; in handle_auth() local
3590 &rad_info); in handle_auth()
3682 res = ieee802_11_set_radius_info(hapd, sta, res, &rad_info); in handle_auth()