/external/llvm-project/llvm/test/CodeGen/AMDGPU/ |
D | andorxorinvimm.ll | 20 ; SI: s_andn2_b32 s{{[0-9]+}}, s{{[0-9]+}}, 50 28 ; SI: s_andn2_b32 s{{[0-9]+}}, s{{[0-9]+}}, 50
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D | andorn2.ll | 7 ; GCN: s_andn2_b32
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D | bfi_int.ll | 11 ; GCN-DAG: s_andn2_b32
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D | insert_vector_dynelt.ll | 146 ; GCN: s_andn2_b32 192 ; GCN: s_andn2_b32
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D | insert_vector_elt.ll | 869 ; SI-NEXT: s_andn2_b32 s5, s6, s4 886 ; VI-NEXT: s_andn2_b32 s5, s6, s4 959 ; SI-NEXT: s_andn2_b32 s5, s6, s4 1000 ; SI-NEXT: s_andn2_b32 s5, s6, s4 1020 ; VI-NEXT: s_andn2_b32 s5, s6, s4 1045 ; SI-NEXT: s_andn2_b32 s5, s6, s4 1062 ; VI-NEXT: s_andn2_b32 s5, s6, s4
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D | atomic_optimizations_pixelshader.ll | 174 ; GFX1032-NEXT: s_andn2_b32 vcc_lo, exec_lo, s4 425 ; GFX1032-NEXT: s_andn2_b32 vcc_lo, exec_lo, s4
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D | wave32.ll | 170 ; GFX1032: s_andn2_b32 exec_lo, exec_lo, s{{[0-9]+}} 237 ; GFX1032: s_andn2_b32 [[MASK1:s[0-9]+]], [[MASK1]], exec_lo 248 ; GFX1032: s_andn2_b32 exec_lo, exec_lo, [[ACC]]
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D | insert_vector_elt.v2i16.ll | 1050 ; GFX9-NEXT: s_andn2_b32 s2, s2, s3 1069 ; VI-NEXT: s_andn2_b32 s1, s2, s0 1088 ; CI-NEXT: s_andn2_b32 s1, s2, s0
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/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/ |
D | andn2.ll | 8 ; GCN-NEXT: s_andn2_b32 s0, s2, s3 18 ; GCN-NEXT: s_andn2_b32 s0, s2, s3 29 ; GCN-NEXT: s_andn2_b32 s0, s2, s3 41 ; GCN-NEXT: s_andn2_b32 s0, s2, s4 42 ; GCN-NEXT: s_andn2_b32 s1, s3, s4 201 ; GCN-NEXT: s_andn2_b32 s0, s2, s3 211 ; GCN-NEXT: s_andn2_b32 s0, s2, s3 222 ; GCN-NEXT: s_andn2_b32 s0, s2, s3 234 ; GCN-NEXT: s_andn2_b32 s0, s2, s4 235 ; GCN-NEXT: s_andn2_b32 s1, s3, s4 [all …]
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D | insertelement.i16.ll | 17 ; GFX9-NEXT: s_andn2_b32 s0, s0, s1 35 ; GFX8-NEXT: s_andn2_b32 s0, s0, s1 53 ; GFX7-NEXT: s_andn2_b32 s0, s0, s1 136 ; GFX9-NEXT: s_andn2_b32 s0, s0, s2 154 ; GFX8-NEXT: s_andn2_b32 s0, s0, s1 171 ; GFX7-NEXT: s_andn2_b32 s0, s0, s1 621 ; GFX9-NEXT: s_andn2_b32 s3, s3, s5 649 ; GFX8-NEXT: s_andn2_b32 s3, s3, s4 674 ; GFX7-NEXT: s_andn2_b32 s3, s3, s4 1115 ; GFX9-NEXT: s_andn2_b32 s5, s7, s5 [all …]
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D | insertelement.i8.ll | 723 ; GFX9-NEXT: s_andn2_b32 s1, s1, s3 761 ; GFX8-NEXT: s_andn2_b32 s0, s0, s1 799 ; GFX7-NEXT: s_andn2_b32 s0, s0, s1 1474 ; GFX9-NEXT: s_andn2_b32 s3, s3, s5 1548 ; GFX8-NEXT: s_andn2_b32 s3, s3, s5 1620 ; GFX7-NEXT: s_andn2_b32 s3, s3, s5 1894 ; GFX9-NEXT: s_andn2_b32 s3, s3, s6 1961 ; GFX8-NEXT: s_andn2_b32 s3, s3, s4 2027 ; GFX7-NEXT: s_andn2_b32 s3, s3, s4 3150 ; GFX9-NEXT: s_andn2_b32 s5, s7, s5 [all …]
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D | shl-ext-reduce.ll | 11 ; GCN-NEXT: s_andn2_b32 s0, s0, -2.0
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/external/llvm/test/MC/AMDGPU/ |
D | sop2.s | 67 s_andn2_b32 s2, s4, s6 label
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/external/llvm-project/llvm/test/MC/AMDGPU/ |
D | sop2.s | 96 s_andn2_b32 s2, s4, s6 label
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/external/llvm/test/MC/Disassembler/AMDGPU/ |
D | sop2_vi.txt | 21 # VI: s_andn2_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x89]
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/external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/ |
D | sop2_vi.txt | 21 # VI: s_andn2_b32 s2, s4, s6 ; encoding: [0x04,0x06,0x02,0x89]
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D | gfx8_dasm_all.txt | 16980 # CHECK: s_andn2_b32 s5, s1, s2 ; encoding: [0x01,0x02,0x05,0x89] 16983 # CHECK: s_andn2_b32 s101, s1, s2 ; encoding: [0x01,0x02,0x65,0x89] 16986 # CHECK: s_andn2_b32 flat_scratch_lo, s1, s2 ; encoding: [0x01,0x02,0x66,0x89] 16989 # CHECK: s_andn2_b32 flat_scratch_hi, s1, s2 ; encoding: [0x01,0x02,0x67,0x89] 16992 # CHECK: s_andn2_b32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0x6a,0x89] 16995 # CHECK: s_andn2_b32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0x6b,0x89] 16998 # CHECK: s_andn2_b32 tba_lo, s1, s2 ; encoding: [0x01,0x02,0x6c,0x89] 17001 # CHECK: s_andn2_b32 tba_hi, s1, s2 ; encoding: [0x01,0x02,0x6d,0x89] 17004 # CHECK: s_andn2_b32 tma_lo, s1, s2 ; encoding: [0x01,0x02,0x6e,0x89] 17007 # CHECK: s_andn2_b32 tma_hi, s1, s2 ; encoding: [0x01,0x02,0x6f,0x89] [all …]
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D | gfx10_dasm_all.txt | 9362 # GFX10: s_andn2_b32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0x7f,0x8a] 9365 # GFX10: s_andn2_b32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0x7e,0x8a] 9368 # GFX10: s_andn2_b32 m0, s1, s2 ; encoding: [0x01,0x02,0x7c,0x8a] 9371 # GFX10: s_andn2_b32 s0, -1, s2 ; encoding: [0xc1,0x02,0x00,0x8a] 9374 # GFX10: s_andn2_b32 s0, -4.0, s2 ; encoding: [0xf7,0x02,0x00,0x8a] 9377 # GFX10: s_andn2_b32 s0, 0, s2 ; encoding: [0x80,0x02,0x00,0x8a] 9380 # GFX10: s_andn2_b32 s0, 0.5, s2 ; encoding: [0xf0,0x02,0x00,0x8a] 9383 # GFX10: s_andn2_b32 s0, 0x3f717273, s2 ; encoding: [0xff,0x02,0x00,0x8a,0x73,0x72,0x71,0x… 9386 # GFX10: s_andn2_b32 s0, 0xaf123456, s2 ; encoding: [0xff,0x02,0x00,0x8a,0x56,0x34,0x12,0x… 9389 # GFX10: s_andn2_b32 s0, exec_hi, s2 ; encoding: [0x7f,0x02,0x00,0x8a] [all …]
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D | gfx9_dasm_all.txt | 15315 # CHECK: s_andn2_b32 s5, s1, s2 ; encoding: [0x01,0x02,0x05,0x89] 15318 # CHECK: s_andn2_b32 s101, s1, s2 ; encoding: [0x01,0x02,0x65,0x89] 15321 # CHECK: s_andn2_b32 flat_scratch_lo, s1, s2 ; encoding: [0x01,0x02,0x66,0x89] 15324 # CHECK: s_andn2_b32 flat_scratch_hi, s1, s2 ; encoding: [0x01,0x02,0x67,0x89] 15327 # CHECK: s_andn2_b32 vcc_lo, s1, s2 ; encoding: [0x01,0x02,0x6a,0x89] 15330 # CHECK: s_andn2_b32 vcc_hi, s1, s2 ; encoding: [0x01,0x02,0x6b,0x89] 15333 # CHECK: s_andn2_b32 m0, s1, s2 ; encoding: [0x01,0x02,0x7c,0x89] 15336 # CHECK: s_andn2_b32 exec_lo, s1, s2 ; encoding: [0x01,0x02,0x7e,0x89] 15339 # CHECK: s_andn2_b32 exec_hi, s1, s2 ; encoding: [0x01,0x02,0x7f,0x89] 15342 # CHECK: s_andn2_b32 s5, s101, s2 ; encoding: [0x65,0x02,0x05,0x89] [all …]
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/external/mesa3d/src/amd/compiler/ |
D | aco_ssa_elimination.cpp | 134 case aco_opcode::s_andn2_b32: in is_empty_block()
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D | aco_optimizer.cpp | 2201 instr->opcode = aco_opcode::s_andn2_b32; in combine_salu_n2() 2908 if (instr->opcode == aco_opcode::s_andn2_b32 || instr->opcode == aco_opcode::s_andn2_b64) in combine_instruction()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
D | SOPInstructions.td | 504 def S_ANDN2_B32 : SOP2_32 <"s_andn2_b32",
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/external/llvm-project/llvm/lib/Target/AMDGPU/ |
D | SOPInstructions.td | 557 def S_ANDN2_B32 : SOP2_32 <"s_andn2_b32",
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/external/llvm/lib/Target/AMDGPU/ |
D | SIInstructions.td | 262 defm S_ANDN2_B32 : SOP2_32 <sop2<0x14, 0x12>, "s_andn2_b32", []>;
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/external/llvm-project/llvm/docs/AMDGPU/ |
D | AMDGPUAsmGFX7.rst | 511 …s_andn2_b32 :ref:`sdst<amdgpu_synid7_sdst32_1>`, :ref:`ssrc0<amdgpu_synid7_…
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