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Searched refs:s_or_b64 (Results 1 – 25 of 106) sorted by relevance

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/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Datomicrmw-nand.ll21 ; GCN-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
25 ; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
49 ; GCN-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
53 ; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
78 ; GCN-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
82 ; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
Dcollapse-endcf.ll11 ; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC]]
46 ; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_INNER]]
49 ; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_OUTER]]
95 ; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_OUTER]]
138 ; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_INNER_IF_OUTER_ELSE]]
150 ; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC_ELSE]]
151 ; GCN: s_or_b64 exec, exec, [[SAVEEXEC_OUTER3]]
195 ; GCN-NEXT: s_or_b64 exec, exec, [[SAVEEXEC]]
217 ; GCN: s_or_b64 exec, exec, [[SAVEEXEC_OUTER:s\[[0-9:]+\]]]
220 ; GCN: s_or_b64 exec, exec, s{{\[[0-9]+:[0-9]+\]}}
[all …]
Dendcf-loop-header.ll4 ; loop block. This intrinsic will be lowered to s_or_b64 by the code
10 ; CHECK: s_or_b64 exec, exec
13 ; CHECK-NOT: s_or_b64 exec, exec
Di1-copy-from-loop.ll14 ; SI-NEXT: s_or_b64 exec, exec, s[14:15]
18 ; SI-NEXT: s_or_b64 s[4:5], s[14:15], s[4:5]
21 ; SI-NEXT: s_or_b64 s[8:9], s[8:9], s[12:13]
26 ; SI-NEXT: s_or_b64 s[10:11], s[10:11], exec
46 ; SI-NEXT: s_or_b64 exec, exec, s[4:5]
Dloop_break.ll47 ; GCN-NEXT: s_or_b64 s[4:5], s[4:5], exec
57 ; GCN-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
61 ; GCN-NEXT: s_or_b64 s[0:1], s[8:9], s[0:1]
126 ; GCN-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
136 ; GCN-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]
141 ; GCN-NEXT: s_or_b64 s[0:1], s[8:9], s[0:1]
145 ; GCN-NEXT: s_or_b64 exec, exec, s[0:1]
221 ; GCN-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
231 ; GCN-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
236 ; GCN-NEXT: s_or_b64 s[0:1], s[8:9], s[0:1]
[all …]
Ddivergent-branch-uniform-condition.ll32 ; ISA-NEXT: s_or_b64 exec, exec, s[8:9]
38 ; ISA-NEXT: s_or_b64 s[2:3], s[10:11], s[2:3]
41 ; ISA-NEXT: s_or_b64 s[4:5], s[4:5], s[8:9]
46 ; ISA-NEXT: s_or_b64 s[6:7], s[6:7], exec
60 ; ISA-NEXT: s_or_b64 exec, exec, s[2:3]
66 ; ISA-NEXT: s_or_b64 exec, exec, s[0:1]
Dmultilevel-break.ll54 ; GCN-NEXT: s_or_b64 exec, exec, s[4:5]
56 ; GCN-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
68 ; GCN-NEXT: s_or_b64 exec, exec, s[8:9]
70 ; GCN-NEXT: s_or_b64 s[4:5], s[8:9], s[4:5]
79 ; GCN-NEXT: s_or_b64 s[2:3], s[2:3], exec
80 ; GCN-NEXT: s_or_b64 s[6:7], s[6:7], exec
89 ; GCN-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
191 ; GCN-NEXT: s_or_b64 s[0:1], s[6:7], s[0:1]
194 ; GCN-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
242 ; GCN-NEXT: s_or_b64 s[6:7], s[6:7], s[10:11]
[all …]
Datomic_optimizations_pixelshader.ll34 ; GFX7-NEXT: s_or_b64 exec, exec, s[10:11]
39 ; GFX7-NEXT: s_or_b64 exec, exec, s[8:9]
67 ; GFX8-NEXT: s_or_b64 exec, exec, s[10:11]
72 ; GFX8-NEXT: s_or_b64 exec, exec, s[8:9]
100 ; GFX9-NEXT: s_or_b64 exec, exec, s[10:11]
105 ; GFX9-NEXT: s_or_b64 exec, exec, s[8:9]
134 ; GFX1064-NEXT: s_or_b64 exec, exec, s[28:29]
139 ; GFX1064-NEXT: s_or_b64 exec, exec, s[8:9]
247 ; GFX8-NEXT: s_or_b64 exec, exec, s[10:11]
253 ; GFX8-NEXT: s_or_b64 exec, exec, s[8:9]
[all …]
Dloop_exit_with_xor.ll11 ; GCN: s_or_b64 [[REG3:[^ ,]*]], [[REG2]],
41 ; GCN: s_or_b64 [[REG2:[^ ,]*]], [[REG1]],
66 ; GCN: s_or_b64 [[REG3]], [[REG2]],
Dsi-annotate-cf.ll19 ; SI-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
23 ; SI-NEXT: s_or_b64 exec, exec, s[0:1]
43 ; FLAT-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
47 ; FLAT-NEXT: s_or_b64 exec, exec, s[0:1]
82 ; SI-NEXT: s_or_b64 exec, exec, s[6:7]
86 ; SI-NEXT: s_or_b64 s[2:3], s[0:1], s[2:3]
106 ; FLAT-NEXT: s_or_b64 exec, exec, s[6:7]
110 ; FLAT-NEXT: s_or_b64 s[2:3], s[0:1], s[2:3]
Dshift-i128.ll195 ; GCN-NEXT: s_or_b64 s[10:11], s[0:1], s[10:11]
232 ; GCN-NEXT: s_or_b64 s[10:11], s[0:1], s[10:11]
274 ; GCN-NEXT: s_or_b64 s[6:7], s[6:7], s[0:1]
462 ; GCN-NEXT: s_or_b64 s[0:1], s[16:17], s[18:19]
464 ; GCN-NEXT: s_or_b64 s[6:7], s[24:25], s[6:7]
483 ; GCN-NEXT: s_or_b64 s[6:7], s[10:11], s[6:7]
485 ; GCN-NEXT: s_or_b64 s[2:3], s[20:21], s[22:23]
531 ; GCN-NEXT: s_or_b64 s[6:7], s[24:25], s[6:7]
533 ; GCN-NEXT: s_or_b64 s[0:1], s[16:17], s[18:19]
553 ; GCN-NEXT: s_or_b64 s[6:7], s[8:9], s[6:7]
[all …]
Dselect-opt.ll74 ; GCN: s_or_b64 vcc, vcc, [[CMP1]]
91 ; GCN: s_or_b64 vcc, vcc, [[CMP1]]
107 ; GCN: s_or_b64 vcc, vcc, [[CMP1]]
123 ; GCN: s_or_b64 vcc, vcc, [[CMP1]]
Dsgpr-control-flow.ll129 ; SI-NEXT: s_or_b64 exec, exec, s[2:3]
175 ; SI-NEXT: s_or_b64 s[0:1], s[0:1], s[8:9]
192 ; SI-NEXT: s_or_b64 s[0:1], s[0:1], s[6:7]
194 ; SI-NEXT: s_or_b64 exec, exec, s[2:3]
Datomic_optimizations_local_pointer.ll38 ; GFX7LESS-NEXT: s_or_b64 exec, exec, s[4:5]
67 ; GFX8-NEXT: s_or_b64 exec, exec, s[4:5]
96 ; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]
128 ; GFX1064-NEXT: s_or_b64 exec, exec, s[4:5]
200 ; GFX7LESS-NEXT: s_or_b64 exec, exec, s[0:1]
233 ; GFX8-NEXT: s_or_b64 exec, exec, s[6:7]
265 ; GFX9-NEXT: s_or_b64 exec, exec, s[6:7]
301 ; GFX1064-NEXT: s_or_b64 exec, exec, s[6:7]
409 ; GFX8-NEXT: s_or_b64 exec, exec, s[2:3]
459 ; GFX9-NEXT: s_or_b64 exec, exec, s[2:3]
[all …]
Dbfi_int.ll128 ; GCN: s_or_b64
169 ; GCN: s_or_b64
171 ; GCN: s_or_b64
/external/llvm/test/CodeGen/AMDGPU/
Dendcf-loop-header.ll4 ; loop block. This intrinsic will be lowered to s_or_b64 by the code
10 ; CHECK: s_or_b64 exec, exec
13 ; CHECK-NOT: s_or_b64 exec, exec
Dsi-lower-control-flow-unreachable-block.ll9 ; GCN: s_or_b64 exec, exec
34 ; GCN: s_or_b64 exec, exec
Dvalu-i1.ll55 ; SI: s_or_b64 exec, exec, [[BR_SREG]]
139 ; SI: s_or_b64 [[TMP:s\[[0-9]+:[0-9]+\]]], [[CMP]], [[COND_STATE]]
142 ; SI: s_or_b64 exec, exec, [[ORNEG2]]
143 ; SI: s_or_b64 [[COND_STATE]], [[ORNEG2]], [[TMP]]
148 ; SI: s_or_b64 exec, exec, [[COND_STATE]]
Dcgp-addressing-modes.ll45 ; GCN: s_or_b64 exec
72 ; GCN: s_or_b64 exec
99 ; GCN: s_or_b64 exec
235 ; GCN: s_or_b64 exec, exec
264 ; GCN: s_or_b64 exec, exec
297 ; GCN: s_or_b64 exec, exec
329 ; GCN: s_or_b64 exec, exec
360 ; GCN: s_or_b64 exec, exec
390 ; GCN: s_or_b64 exec, exec
428 ; GCN: s_or_b64 exec, exec
Dsi-annotate-cf.ll8 ; SI: s_or_b64
30 ; FIXME: This could be folded into the s_or_b64 instruction
36 ; SI: s_or_b64 [[BREAK:s\[[0-9]+:[0-9]+\]]], vcc, [[ZERO]]
Dsi-annotate-cfg-loop-assert.ll6 ; CHECK s_or_b64 exec, exec
Dor.ll87 ; SI: s_or_b64
158 ; SI: s_or_b64 s[{{[0-9]+:[0-9]+}}], vcc, s[{{[0-9]+:[0-9]+}}]
171 ; SI: s_or_b64 s[{{[0-9]+:[0-9]+}}], vcc, s[{{[0-9]+:[0-9]+}}]
/external/mesa3d/src/amd/compiler/tests/
Dtest_optimizer.cpp175 writeout(0, bld.sop2(aco_opcode::s_or_b64, bld.def(bld.lm), bld.def(s1, scc),
181 writeout(1, bld.sop2(aco_opcode::s_or_b64, bld.def(bld.lm), bld.def(s1, scc),
187 writeout(2, bld.sop2(aco_opcode::s_or_b64, bld.def(bld.lm), bld.def(s1, scc),
218 writeout(6, bld.sop2(aco_opcode::s_or_b64, bld.def(bld.lm), bld.def(s1, scc),
226 writeout(7, bld.sop2(aco_opcode::s_or_b64, bld.def(bld.lm), bld.def(s1, scc),
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Ddivergent-control-flow.ll17 ; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
44 ; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
73 ; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
104 ; CHECK-NEXT: s_or_b64 exec, exec, s[4:5]
211 ; CHECK-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
Dorn2.ll474 ; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
482 ; GFX9-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
509 ; GFX6-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1]
517 ; GFX9-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
544 ; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]
552 ; GFX9-NEXT: s_or_b64 s[0:1], s[2:3], s[4:5]
591 ; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]
592 ; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]
600 ; GFX9-NEXT: s_or_b64 s[0:1], s[2:3], s[6:7]
601 ; GFX9-NEXT: s_or_b64 s[2:3], s[4:5], s[6:7]

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