Home
last modified time | relevance | path

Searched refs:sp_reg (Results 1 – 11 of 11) sorted by relevance

/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dregbankselect-dyn-stackalloc.mir23 ; WAVE64: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
30 ; WAVE32: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
53 ; WAVE64: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
60 ; WAVE32: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
83 ; WAVE64: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
90 ; WAVE32: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
113 ; WAVE64: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
120 ; WAVE32: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
143 ; WAVE64: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
150 ; WAVE32: [[COPY1:%[0-9]+]]:sgpr(p5) = COPY $sp_reg
[all …]
Dirtranslator-call-sret.ll52 ; GCN: [[COPY21:%[0-9]+]]:_(p5) = COPY $sp_reg
Dirtranslator-call.ll2525 ; CHECK: [[COPY20:%[0-9]+]]:_(p5) = COPY $sp_reg
2617 ; CHECK: [[COPY20:%[0-9]+]]:_(p5) = COPY $sp_reg
2710 ; CHECK: [[COPY20:%[0-9]+]]:_(p5) = COPY $sp_reg
3485 ; CHECK: [[COPY20:%[0-9]+]]:_(p5) = COPY $sp_reg
3580 ; CHECK: [[COPY20:%[0-9]+]]:_(p5) = COPY $sp_reg
3682 ; CHECK: [[COPY21:%[0-9]+]]:_(p5) = COPY $sp_reg
3790 ; CHECK: [[COPY21:%[0-9]+]]:_(p5) = COPY $sp_reg
4028 ; CHECK: [[COPY20:%[0-9]+]]:_(p5) = COPY $sp_reg
4510 ; CHECK: [[COPY20:%[0-9]+]]:_(p5) = COPY $sp_reg
Dirtranslator-call-implicit-args.ll266 ; GFX900: [[COPY20:%[0-9]+]]:_(p5) = COPY $sp_reg
351 ; GFX908: [[COPY20:%[0-9]+]]:_(p5) = COPY $sp_reg
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dsplitkit-nolivesubranges.mir27 …; CHECK: SI_SPILL_S64_SAVE renamable $sgpr0_sgpr1, %stack.0, implicit $exec, implicit $sp_reg :: (…
29 … $sgpr0_sgpr1 = SI_SPILL_S64_RESTORE %stack.0, implicit $exec, implicit $sp_reg :: (load 8 from %s…
/external/llvm-project/llvm/test/CodeGen/MIR/AMDGPU/
Dmachine-function-info-no-ir.mir94 # FULL-NEXT: stackPtrOffsetReg: '$sp_reg'
135 # FULL-NEXT: stackPtrOffsetReg: '$sp_reg'
177 # FULL-NEXT: stackPtrOffsetReg: '$sp_reg'
211 # FULL-NEXT: stackPtrOffsetReg: '$sp_reg'
/external/llvm-project/lldb/source/Plugins/ABI/Hexagon/
DABISysV_hexagon.cpp1074 uint32_t sp_reg = reg_ctx->ConvertRegisterKindToRegisterNumber( in PrepareTrivialCall() local
1076 if (sp_reg == LLDB_INVALID_REGNUM) in PrepareTrivialCall()
1153 reg_ctx->WriteRegisterFromUnsigned(sp_reg, sp); in PrepareTrivialCall()
/external/llvm-project/lldb/source/Plugins/ABI/ARC/
DABISysV_arc.cpp214 uint32_t sp_reg = reg_ctx->ConvertRegisterKindToRegisterNumber( in PrepareTrivialCall() local
216 if (sp_reg == LLDB_INVALID_REGNUM) in PrepareTrivialCall()
303 reg_ctx->WriteRegisterFromUnsigned(sp_reg, sp); in PrepareTrivialCall()
/external/llvm-project/lldb/source/Plugins/Instruction/ARM/
DEmulateInstructionARM.cpp978 RegisterInfo sp_reg; in EmulatePUSH() local
979 GetRegisterInfo(eRegisterKindDWARF, dwarf_sp, sp_reg); in EmulatePUSH()
983 context.SetRegisterToRegisterPlusOffset(reg_info, sp_reg, addr - sp); in EmulatePUSH()
995 context.SetRegisterToRegisterPlusOffset(reg_info, sp_reg, addr - sp); in EmulatePUSH()
1105 RegisterInfo sp_reg; in EmulatePOP() local
1106 GetRegisterInfo(eRegisterKindDWARF, dwarf_sp, sp_reg); in EmulatePOP()
1122 context.SetRegisterPlusOffset(sp_reg, addr - sp); in EmulatePOP()
1192 RegisterInfo sp_reg; in EmulateADDRdSPImm() local
1193 GetRegisterInfo(eRegisterKindDWARF, dwarf_sp, sp_reg); in EmulateADDRdSPImm()
1194 context.SetRegisterPlusOffset(sp_reg, sp_offset); in EmulateADDRdSPImm()
[all …]
/external/llvm-project/llvm/test/CodeGen/AVR/inline-asm/
Dinline-asm.ll58 ; define void @sp_reg(i16 %var)
/external/google-breakpad/src/third_party/libdisasm/swig/
Dlibdisasm_oop.i1028 unsigned int sp_reg() { in sp_reg() function