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/external/llvm-project/llvm/test/CodeGen/ARM/
Darm-storebytesmerge.ll4 define arm_aapcs_vfpcc void @test(i8* %v50) {
97 %v190 = getelementptr inbounds i8, i8* %v50, i32 394
99 %v191 = getelementptr inbounds i8, i8* %v50, i32 395
101 %v192 = getelementptr inbounds i8, i8* %v50, i32 396
103 %v193 = getelementptr inbounds i8, i8* %v50, i32 397
105 %v194 = getelementptr inbounds i8, i8* %v50, i32 398
107 %v195 = getelementptr inbounds i8, i8* %v50, i32 399
109 %v196 = getelementptr inbounds i8, i8* %v50, i32 400
111 %v197 = getelementptr inbounds i8, i8* %v50, i32 401
113 %v198 = getelementptr inbounds i8, i8* %v50, i32 402
[all …]
/external/llvm-project/llvm/test/CodeGen/Hexagon/
Dwcsrtomb.ll100 %v50 = call i32 @f2(i8* %v48, i32 %v49, %s.0* %v4) #1
101 %v51 = icmp slt i32 %v50, 0
109 %v53 = icmp ult i32 %v32, %v50
119 %v54 = call i8* @f4(i8* %v31, i8* %v7, i32 %v50) #1
123 %v55 = icmp sgt i32 %v50, 0
127 %v56 = add nsw i32 %v50, -1
136 %v61 = add i32 %v60, %v50
140 %v62 = add i32 %v50, %v33
142 %v64 = getelementptr inbounds i8, i8* %v31, i32 %v50
143 %v65 = sub i32 %v32, %v50
[all …]
Dconstext-replace.ll138 %v50 = load i32, i32* @g0, align 4
139 store i32 %v50, i32* %v44, align 4
140 %v51 = getelementptr inbounds [13595 x i32], [13595 x i32]* @g1, i32 0, i32 %v50
142 %v52 = getelementptr inbounds [13595 x i32], [13595 x i32]* @g2, i32 0, i32 %v50
Dswp-phi-dep1.ll72 %v50 = zext i8 %v43 to i32
78 %v56 = add i32 %v50, %v48
86 %v64 = sub i32 %v48, %v50
Dregisterscavenger-fail1.ll137 %v50 = load double, double* %v47, align 8, !tbaa !0
138 %v51 = fcmp olt double %v37, %v50
139 %v52 = select i1 %v51, double %v50, double %v37
145 %v58 = fcmp ogt double %v38, %v50
146 %v59 = select i1 %v58, double %v50, double %v38
Dswp-epilog-phi5.ll110 %v50 = phi i8* [ %v45, %b4 ], [ %v76, %b5 ]
114 %v54 = phi i8* [ %v18, %b4 ], [ %v50, %b5 ]
131 store i8 %v69, i8* %v50, align 1
138 %v76 = getelementptr inbounds i8, i8* %v50, i32 2
Dbug-allocframe-size.ll99 %v50 = load float, float* %v49, align 4
100 ret float %v50
Dswp-phi-chains.ll50 %v9 = phi i32 [ %v6, %b0 ], [ %v50, %b1 ]
94 %v50 = tail call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32 %v47, i32 %v43, i32 %v49)
95 store i32 %v50, i32* @g3, align 4
Dvect-set_cc_v2i32.ll99 %v50 = load i32, i32* %v6, align 8
100 %v51 = shl i32 %v50, 16
102 %v53 = and i32 %v50, -65536
Dearly-if-merge-loop.ll67 %v50 = add nuw nsw i32 %v13, 2
68 %v51 = getelementptr inbounds i32, i32* %v3, i32 %v50
Dreg-scavengebug-2.ll16 %v1 = phi i32 [ 0, %b1 ], [ %v50, %b4 ]
73 %v50 = add nsw i32 %v1, 1
74 %v51 = icmp slt i32 %v50, 0
Dvect_setcc_v2i16.ll89 %v50 = bitcast i16* %v46 to <4 x i16>*
90 store <4 x i16> %v49, <4 x i16>* %v50, align 8
Dexpand-condsets.ll79 %v50 = getelementptr inbounds i32, i32* %a2, i32 %v8
80 store i32 %v41, i32* %v50, align 4, !tbaa !0
Dbkfir.ll72 %v50 = trunc i32 %v49 to i16
81 %v56 = phi i16 [ %v50, %b4 ], [ 0, %b2 ]
Dsdr-reg-profit.ll74 %v50 = icmp ult i32 %v45, 30
75 br i1 %v50, label %b8, label %b51
Dv6-inlasm1.ll80 %v50 = load <16 x i32>, <16 x i32>* %v14, align 64
82 %v52 = call <16 x i32> @llvm.hexagon.V6.vrdelta(<16 x i32> %v50, <16 x i32> %v51)
Dreg_seq.ll66 %v50 = load i16, i16* %v49, align 2, !tbaa !3
83 %v67 = zext i16 %v50 to i64
Dswp-disable-Os.ll64 %v50 = add i32 %v45, %v49
69 %v55 = add i32 %v50, %v54
Dregalloc-block-overlap.ll133 %v50 = tail call <32 x i32> @llvm.hexagon.V6.vmpyiewuh.128B(<32 x i32> undef, <32 x i32> %v49) #2
134 %v51 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> undef, <32 x i32> %v50) #2
Dswp-resmii-1.ll73 %v50 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> %v47, <16 x i32> %v46)
76 store <16 x i32> %v50, <16 x i32>* %v33, align 64
/external/llvm-project/llvm/test/MC/AMDGPU/
Dgfx1030_new.s87 image_bvh_intersect_ray v[39:42], [v50, v46, v23, v17, v16, v15, v21, v20, v19, v37, v40], s[12:15]
90 image_bvh_intersect_ray v[39:42], [v50, v46, v23, v17, v16, v15, v21, v20], s[12:15] a16
93 image_bvh64_intersect_ray v[39:42], [v50, v46, v23, v17, v16, v15, v21, v20, v19, v37, v40, v42], s…
96 image_bvh64_intersect_ray v[39:42], [v50, v46, v23, v17, v16, v15, v21, v20, v19], s[12:15] a16
/external/llvm-project/llvm/test/MC/VE/
DVFMF.s46 # CHECK-INST: vfmk.d.nan %vm1, %v50, %vm14
48 vfmk.d.nan %vm1, %v50, %vm14
114 # CHECK-INST: pvfmk.s.up.nan %vm1, %v50, %vm14
116 vfmk.s.nan %vm1, %v50, %vm14
182 # CHECK-INST: pvfmk.s.up.nan %vm1, %v50, %vm14
184 pvfmk.s.up.nan %vm1, %v50, %vm14
250 # CHECK-INST: pvfmk.s.lo.nan %vm1, %v50, %vm14
252 pvfmk.s.lo.nan %vm1, %v50, %vm14
/external/llvm-project/llvm/test/CodeGen/Hexagon/autohvx/
Dfloat-cost.ll71 %v50 = fadd float %v49, %v44
75 %v54 = fsub float %v53, %v50
77 %v56 = fadd float %v50, %v55
/external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
Dgfx1030_dasm_new.txt78 # GFX10: image_bvh_intersect_ray v[39:42], [v50, v46, v23, v17, v16, v15, v21, v20, v19, v37, v40],…
81 # GFX10: image_bvh_intersect_ray v[39:42], [v50, v46, v23, v17, v16, v15, v21, v20], s[12:15] a16
84 # GFX10: image_bvh64_intersect_ray v[39:42], [v50, v46, v23, v17, v16, v15, v21, v20, v19, v37, v40…
87 # GFX10: image_bvh64_intersect_ray v[39:42], [v50, v46, v23, v17, v16, v15, v21, v20, v19], s[12:15…
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dreserve-vgpr-for-sgpr-spill.ll29 ,~{v50},~{v51},~{v52},~{v53},~{v54},~{v55},~{v56},~{v57},~{v58},~{v59}
74 ,~{v50},~{v51},~{v52},~{v53},~{v54},~{v55},~{v56},~{v57},~{v58},~{v59}
116 ,~{v50},~{v51},~{v52},~{v53},~{v54},~{v55},~{v56},~{v57},~{v58},~{v59}
165 ,~{v50},~{v51},~{v52},~{v53},~{v54},~{v55},~{v56},~{v57},~{v58},~{v59}

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