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Searched refs:v_cndmask_b32 (Results 1 – 25 of 60) sorted by relevance

123

/external/llvm-project/llvm/test/CodeGen/AMDGPU/
Dload-select-ptr.ll12 ; GCN: v_cndmask_b32
13 ; GCN: v_cndmask_b32
38 ; GCN: v_cndmask_b32
39 ; GCN: v_cndmask_b32
53 ; GCN: v_cndmask_b32
54 ; GCN: v_cndmask_b32
71 ; GCN: v_cndmask_b32
72 ; GCN: v_cndmask_b32
Dselect64.ll21 ; SI: v_cndmask_b32
22 ; SI-NOT: v_cndmask_b32
34 ; SI: v_cndmask_b32
35 ; SI-NOT: v_cndmask_b32
47 ; SI: v_cndmask_b32
48 ; SI-NOT: v_cndmask_b32
Dinsert_vector_dynelt.ll123 ; GCN-NOT: v_cndmask_b32
141 ; GCN-NOT: v_cndmask_b32
187 ; GCN-NOT: v_cndmask_b32
203 ; GCN-NOT: v_cndmask_b32
292 ; GCN-COUNT-10: v_cndmask_b32
400 ; GCN-COUNT-2: v_cndmask_b32
402 ; GCN-COUNT-2: v_cndmask_b32
404 ; GCN-COUNT-2: v_cndmask_b32
406 ; GCN-COUNT-2: v_cndmask_b32
408 ; GCN-COUNT-2: v_cndmask_b32
[all …]
Dextract-subvector.ll43 ; GCN-COUNT-2: v_cndmask_b32
64 ; GCN-COUNT-4: v_cndmask_b32
85 ; GCN-COUNT-8: v_cndmask_b32
106 ; GCN-COUNT-2: v_cndmask_b32
127 ; GCN-COUNT-4: v_cndmask_b32
148 ; GCN-COUNT-8: v_cndmask_b32
Dselect-i1.ll7 ; GCN: v_cndmask_b32
8 ; GCN-NOT: v_cndmask_b32
Dllvm.rint.f64.ll11 ; SI: v_cndmask_b32
12 ; SI: v_cndmask_b32
Doptimize-negated-cond.ll7 ; GCN-NOT: v_cndmask_b32
41 ; GCN-NOT: v_cndmask_b32
Dzero_extend.ll22 ; GCN: v_cndmask_b32
41 ; GCN: v_cndmask_b32
Dselect-vectors.ll9 ; SI: v_cndmask_b32
12 ; GFX9: v_cndmask_b32
17 ; VI: v_cndmask_b32
18 ; VI: v_cndmask_b32
72 ; SI: v_cndmask_b32
100 ; GCN: v_cndmask_b32
373 ; GCN: v_cndmask_b32
Dfceil64.ll29 ; SI-DAG: v_cndmask_b32
30 ; SI: v_cndmask_b32
Dcndmask-no-def-vcc.ll5 ; Produces error after adding an implicit def to v_cndmask_b32
Dindirect-addressing-si-pregfx9.ll23 ; GCN-COUNT-32: v_cndmask_b32
/external/llvm/test/CodeGen/AMDGPU/
Dselect64.ll19 ; CHECK: v_cndmask_b32
20 ; CHECK-NOT: v_cndmask_b32
30 ; CHECK: v_cndmask_b32
31 ; CHECK-NOT: v_cndmask_b32
41 ; CHECK: v_cndmask_b32
42 ; CHECK-NOT: v_cndmask_b32
Dvselect.ll50 ; SI: v_cndmask_b32
51 ; SI: v_cndmask_b32
52 ; SI: v_cndmask_b32
53 ; SI: v_cndmask_b32
Dzero_extend.ll22 ; SI: v_cndmask_b32
34 ; SI: v_cndmask_b32
Dselect-i1.ll7 ; SI: v_cndmask_b32
8 ; SI-NOT: v_cndmask_b32
Dllvm.rint.f64.ll11 ; SI: v_cndmask_b32
12 ; SI: v_cndmask_b32
Dfceil64.ll28 ; SI-DAG: v_cndmask_b32
29 ; SI: v_cndmask_b32
Dcndmask-no-def-vcc.ll5 ; Produces error after adding an implicit def to v_cndmask_b32
/external/llvm-project/llvm/test/MC/AMDGPU/
Dvop-err.s96 v_cndmask_b32 v0, s1, v2, vcc label
99 v_cndmask_b32 v0, flat_scratch_lo, v2, vcc label
102 v_cndmask_b32 v0, flat_scratch_hi, v2, vcc label
105 v_cndmask_b32 v0, exec_lo, v2, vcc label
108 v_cndmask_b32 v0, exec_hi, v2, vcc label
Dgfx9-vop2be-literal.s6 v_cndmask_b32 v0, 12345, v1, vcc label
Dgfx10-vop2be-literal.s6 v_cndmask_b32 v0, 12345, v1, vcc_lo label
Dlds_direct.s35 v_cndmask_b32 v0, src_lds_direct, v0, vcc label
/external/llvm/test/MC/AMDGPU/
Dvop2-err.s11 v_cndmask_b32 v1, v2, v3 label
Dvop3.s201 v_cndmask_b32 v1, v3, v5, s[4:5] label

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