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Searched refs:v_mul_i32_i24_e32 (Results 1 – 20 of 20) sorted by relevance

/external/llvm-project/llvm/test/MC/AMDGPU/
Dvop2.s49 v_mul_i32_i24_e32 v1, v2, v3 label
59 v_mul_i32_i24_e32 v1, 3, v3 label
64 v_mul_i32_i24_e32 v1, -3, v3 label
79 v_mul_i32_i24_e32 v1, 100, v3 label
84 v_mul_i32_i24_e32 v1, -100, v3 label
93 v_mul_i32_i24_e32 v1, s2, v3 label
175 v_mul_i32_i24_e32 v1, v2, v3 label
Dvop2-err.s16 v_mul_i32_i24_e32 v1, v2, 100 label
20 v_mul_i32_i24_e32 v1, v2, s3 label
/external/llvm-project/llvm/test/CodeGen/AMDGPU/
DcomputeNumSignBits-mul.ll10 ; GFX9-NEXT: v_mul_i32_i24_e32 v0, v0, v1
30 ; GFX9-NEXT: v_mul_i32_i24_e32 v0, v0, v2
79 ; GFX9-NEXT: v_mul_i32_i24_e32 v0, v0, v1
80 ; GFX9-NEXT: v_mul_i32_i24_e32 v1, v2, v3
109 ; GFX9-NEXT: v_mul_i32_i24_e32 v0, v0, v1
110 ; GFX9-NEXT: v_mul_i32_i24_e32 v1, v2, v3
139 ; GFX9-NEXT: v_mul_i32_i24_e32 v0, v0, v1
140 ; GFX9-NEXT: v_mul_i32_i24_e32 v1, v2, v3
Dmul_int24.ll70 ; GCN-DAG: v_mul_i32_i24_e32
106 ; GCN-DAG: v_mul_i32_i24_e32
151 ; GCN: v_mul_i32_i24_e32 v[[VAL_LO:[0-9]+]]
Damdgpu-mul24-knownbits.ll8 ; GCN-NEXT: v_mul_i32_i24_e32 v0, -5, v0
Dtrunc-combine.ll99 ; SI-NEXT: v_mul_i32_i24_e32 v0, s5, v0
117 ; VI-NEXT: v_mul_i32_i24_e32 v2, s1, v2
Didot8s.ll384 ; GFX8-NEXT: v_mul_i32_i24_e32 v3, s8, v3
440 ; GFX9-NEXT: v_mul_i32_i24_e32 v2, s10, v2
496 ; GFX9-DL-NEXT: v_mul_i32_i24_e32 v2, s10, v2
747 ; GFX8-NEXT: v_mul_i32_i24_e32 v3, s9, v3
806 ; GFX9-NEXT: v_mul_i32_i24_e32 v2, s11, v2
865 ; GFX9-DL-NEXT: v_mul_i32_i24_e32 v2, s11, v2
1624 ; GFX7-NEXT: v_mul_i32_i24_e32 v1, s4, v1
1625 ; GFX7-NEXT: v_mul_i32_i24_e32 v2, s13, v2
1626 ; GFX7-NEXT: v_mul_i32_i24_e32 v3, s12, v3
1627 ; GFX7-NEXT: v_mul_i32_i24_e32 v4, s11, v4
[all …]
Dlshl64-to-32.ll128 ; GCN-NEXT: v_mul_i32_i24_e32 v0, -7, v0
Dllvm.amdgcn.buffer.load.ll401 ;CHECK-NEXT: v_mul_i32_i24_e32 v{{[0-9]}}, 0xff, v{{[0-9]}}
416 ;CHECK-NEXT: v_mul_i32_i24_e32 v{{[0-9]}}, 0xff, v{{[0-9]}}
Damdgpu-codegenprepare-idiv.ll4647 ; GCN-NEXT: v_mul_i32_i24_e32 v0, 0x12d8fb, v0
/external/llvm/test/MC/AMDGPU/
Dvop2-err.s19 v_mul_i32_i24_e32 v1, v2, 100 label
23 v_mul_i32_i24_e32 v1, v2, s3 label
Dvop2.s43 v_mul_i32_i24_e32 v1, v2, v3 label
/external/llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/
Dshl-ext-reduce.ll217 ; GFX7-NEXT: v_mul_i32_i24_e32 v1, -7, v0
242 ; GFX8-NEXT: v_mul_i32_i24_e32 v0, -7, v0
257 ; GFX9-NEXT: v_mul_i32_i24_e32 v1, -7, v1
/external/llvm/docs/
DAMDGPUUsage.rst116 v_mul_i32_i24_e32 v1, v2, v3
/external/llvm/test/MC/Disassembler/AMDGPU/
Dvop2_vi.txt27 # VI: v_mul_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0c]
/external/llvm-project/llvm/test/MC/Disassembler/AMDGPU/
Dvop2_vi.txt27 # VI: v_mul_i32_i24_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x0c]
Dgfx8_dasm_all.txt34899 # CHECK: v_mul_i32_i24_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x0c]
34902 # CHECK: v_mul_i32_i24_e32 v255, v1, v2 ; encoding: [0x01,0x05,0xfe,0x0d]
34905 # CHECK: v_mul_i32_i24_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x0c]
34908 # CHECK: v_mul_i32_i24_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x0c]
34911 # CHECK: v_mul_i32_i24_e32 v5, s101, v2 ; encoding: [0x65,0x04,0x0a,0x0c]
34914 # CHECK: v_mul_i32_i24_e32 v5, flat_scratch_lo, v2 ; encoding: [0x66,0x04,0x0a,0x0c]
34917 # CHECK: v_mul_i32_i24_e32 v5, flat_scratch_hi, v2 ; encoding: [0x67,0x04,0x0a,0x0c]
34920 # CHECK: v_mul_i32_i24_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x0c]
34923 # CHECK: v_mul_i32_i24_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x0c]
34926 # CHECK: v_mul_i32_i24_e32 v5, tba_lo, v2 ; encoding: [0x6c,0x04,0x0a,0x0c]
[all …]
Dgfx10_dasm_all.txt88011 # GFX10: v_mul_i32_i24_e32 v255, v1, v2 ; encoding: [0x01,0x05,0xfe,0x13]
88014 # GFX10: v_mul_i32_i24_e32 v5, -1, v2 ; encoding: [0xc1,0x04,0x0a,0x12]
88017 # GFX10: v_mul_i32_i24_e32 v5, -4.0, v2 ; encoding: [0xf7,0x04,0x0a,0x12]
88020 # GFX10: v_mul_i32_i24_e32 v5, 0, v2 ; encoding: [0x80,0x04,0x0a,0x12]
88023 # GFX10: v_mul_i32_i24_e32 v5, 0.5, v2 ; encoding: [0xf0,0x04,0x0a,0x12]
88026 # GFX10: v_mul_i32_i24_e32 v5, 0x3f717273, v2 ; encoding: [0xff,0x04,0x0a,0x12,0x73,0x72,0x71,0x…
88029 # GFX10: v_mul_i32_i24_e32 v5, 0xaf123456, v2 ; encoding: [0xff,0x04,0x0a,0x12,0x56,0x34,0x12,0x…
88032 # GFX10: v_mul_i32_i24_e32 v5, exec_hi, v2 ; encoding: [0x7f,0x04,0x0a,0x12]
88035 # GFX10: v_mul_i32_i24_e32 v5, exec_lo, v2 ; encoding: [0x7e,0x04,0x0a,0x12]
88038 # GFX10: v_mul_i32_i24_e32 v5, m0, v2 ; encoding: [0x7c,0x04,0x0a,0x12]
[all …]
Dgfx9_dasm_all.txt29523 # CHECK: v_mul_i32_i24_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x0c]
29526 # CHECK: v_mul_i32_i24_e32 v255, v1, v2 ; encoding: [0x01,0x05,0xfe,0x0d]
29529 # CHECK: v_mul_i32_i24_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x0c]
29532 # CHECK: v_mul_i32_i24_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x0c]
29535 # CHECK: v_mul_i32_i24_e32 v5, s101, v2 ; encoding: [0x65,0x04,0x0a,0x0c]
29538 # CHECK: v_mul_i32_i24_e32 v5, flat_scratch_lo, v2 ; encoding: [0x66,0x04,0x0a,0x0c]
29541 # CHECK: v_mul_i32_i24_e32 v5, flat_scratch_hi, v2 ; encoding: [0x67,0x04,0x0a,0x0c]
29544 # CHECK: v_mul_i32_i24_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x0c]
29547 # CHECK: v_mul_i32_i24_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x0c]
29550 # CHECK: v_mul_i32_i24_e32 v5, m0, v2 ; encoding: [0x7c,0x04,0x0a,0x0c]
[all …]
/external/llvm-project/llvm/docs/
DAMDGPUUsage.rst8885 v_mul_i32_i24_e32 v1, -3, v3
8886 v_mul_i32_i24_e32 v1, -100, v3