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Searched refs:MI_FLUSH_DW (Results 1 – 10 of 10) sorted by relevance

/external/libdrm/intel/tests/
Dgen7-2d-copy.batch-ref.txt9 0x12300020: 0x13000002: MI_FLUSH_DW post_sync_op='no write'
/external/igt-gpu-tools/tests/i915/
Dgem_double_irq_loop.c77 OUT_BATCH(MI_FLUSH_DW | 1); in dummy_reloc_loop()
Dgem_write_read_ring_switch.c125 OUT_BATCH(MI_FLUSH_DW | 1); in run_test()
/external/mesa3d/src/mesa/drivers/dri/i915/
Dintel_reg.h42 #define MI_FLUSH_DW (CMD_MI | (0x26 << 23) | 2) macro
/external/mesa3d/docs/relnotes/
D17.2.6.rst88 - i965: Program DWord Length in MI_FLUSH_DW
89 - i965/gen8+: Fix the number of dwords programmed in MI_FLUSH_DW
D7.10.rst2900 - i965: Use MI_FLUSH_DW for blt ring flush on sandybridge
/external/igt-gpu-tools/lib/
Di830_reg.h35 #define MI_FLUSH_DW (0x26<<23) macro
Digt_draw.c282 OUT_BATCH(MI_FLUSH_DW | 2); in switch_blt_tiling()
/external/mesa3d/src/mesa/drivers/dri/i965/
Dintel_blit.c91 OUT_BATCH(MI_FLUSH_DW | (n_dwords - 2)); in set_blitter_tiling()
Dbrw_defines.h1437 #define MI_FLUSH_DW (CMD_MI | (0x26 << 23)) macro