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Searched refs:var16 (Results 1 – 25 of 32) sorted by relevance

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/external/llvm/test/CodeGen/AArch64/
Dcode-model-large-abs.ll4 @var16 = global i16 0
32 %val = load i16, i16* @var16
34 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var16
35 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var16
36 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var16
37 ; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var16
Darm64-code-model-large-abs.ll4 @var16 = global i16 0
32 %val = load i16, i16* @var16
34 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g3:var16
35 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var16
36 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var16
37 ; CHECK: movk x[[ADDR_REG]], #:abs_g0_nc:var16
Darm64-elf-globals.ll7 @var16 = external global i16, align 2
34 %val = load i16, i16* @var16, align 2
35 store i16 %new, i16* @var16
38 ; CHECK: adrp x[[HIREG:[0-9]+]], var16
39 ; CHECK: ldrh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16]
40 ; CHECK: strh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16]
42 ; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var16
43 ; CHECK-FAST: ldrh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16]
Datomic-ops.ll11 @var16 = global i16 0
37 %old = atomicrmw add i16* @var16, i16 %offset acquire
39 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
40 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
117 %old = atomicrmw sub i16* @var16, i16 %offset release
119 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
120 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
197 %old = atomicrmw and i16* @var16, i16 %offset monotonic
199 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
200 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Delf-globals-static.ll5 @var16 = external dso_local global i16, align 2
23 %val = load i16, i16* @var16, align 2
24 store i16 %new, i16* @var16
27 ; CHECK: adrp x[[HIREG:[0-9]+]], var16
28 ; CHECK: ldrh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16]
29 ; CHECK: strh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16]
31 ; CHECK-FAST: adrp x[[HIREG:[0-9]+]], var16
32 ; CHECK-FAST: ldrh {{w[0-9]+}}, [x[[HIREG]], :lo12:var16]
Dcode-model-large-abs.ll4 @var16 = global i16 0
32 %val = load i16, i16* @var16
34 ; CHECK: movz x[[ADDR_REG:[0-9]+]], #:abs_g0_nc:var16
35 ; CHECK: movk x[[ADDR_REG]], #:abs_g1_nc:var16
36 ; CHECK: movk x[[ADDR_REG]], #:abs_g2_nc:var16
37 ; CHECK: movk x[[ADDR_REG]], #:abs_g3:var16
Datomic-ops.ll12 @var16 = global i16 0
49 ; OUTLINE_ATOMICS-NEXT: adrp x1, var16
50 ; OUTLINE_ATOMICS-NEXT: add x1, x1, :lo12:var16
54 %old = atomicrmw add i16* @var16, i16 %offset acquire
56 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
57 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
163 ; OUTLINE_ATOMICS-NEXT: adrp x1, var16
164 ; OUTLINE_ATOMICS-NEXT: add x1, x1, :lo12:var16
168 %old = atomicrmw sub i16* @var16, i16 %offset release
170 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
[all …]
Datomic-ops-lse.ll14 @var16 = global i16 0
45 ; OUTLINE-ATOMICS-NEXT: adrp x1, var16
46 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
50 %old = atomicrmw add i16* @var16, i16 %offset seq_cst
52 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
53 ; CHECK: add x[[ADDR:[0-9]+]], [[TMPADDR]], {{#?}}:lo12:var16
169 ; OUTLINE-ATOMICS-NEXT: adrp x1, var16
170 ; OUTLINE-ATOMICS-NEXT: add x1, x1, :lo12:var16
174 %old = atomicrmw or i16* @var16, i16 %offset seq_cst
176 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
[all …]
Dcode-model-tiny-abs.ll4 @var16 = global i16 0
26 %val = load i16, i16* @var16
28 ; CHECK: adr x[[ADDR_REG:[0-9]+]], var16
Delf-globals-pic.ll5 @var16 = external global i16, align 2
24 %val = load i16, i16* @var16, align 2
25 store i16 %new, i16* @var16
/external/llvm-project/llvm/test/MC/AArch64/
Delf-globaladdress.ll10 @var16 = global i16 0
18 %val16 = load i16, i16* @var16
19 store volatile i16 %val16, i16* @var16
46 ; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_ADR_PREL_PG_HI21 var16
47 ; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_LDST16_ABS_LO12_NC var16
/external/llvm/test/MC/AArch64/
Delf-globaladdress.ll10 @var16 = global i16 0
18 %val16 = load i16, i16* @var16
19 store volatile i16 %val16, i16* @var16
46 ; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_ADR_PREL_PG_HI21 var16
47 ; OBJ: 0x{{[0-9,A-F]+}} R_AARCH64_LDST16_ABS_LO12_NC var16
/external/llvm-project/llvm/test/CodeGen/ARM/
Dpreferred-align.ll18 @var16 = global i16 zeroinitializer
20 ; CHECK: .globl var16
Datomic-ops-v8.ll7 @var16 = global i16 0
36 %old = atomicrmw add i16* @var16, i16 %offset acquire
39 ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16
40 ; CHECK: movt r[[ADDR]], :upper16:var16
132 %old = atomicrmw sub i16* @var16, i16 %offset release
135 ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16
136 ; CHECK: movt r[[ADDR]], :upper16:var16
228 %old = atomicrmw and i16* @var16, i16 %offset monotonic
231 ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16
232 ; CHECK: movt r[[ADDR]], :upper16:var16
[all …]
Datomic-ops-m33.ll28 %old = atomicrmw add i16* @var16, i16 %offset acquire
31 ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16
32 ; CHECK: movt r[[ADDR]], :upper16:var16
138 @var16 = global i16 0
/external/llvm/test/CodeGen/ARM/
Dpreferred-align.ll18 @var16 = global i16 zeroinitializer
20 ; CHECK: .globl var16
Datomic-ops-v8.ll7 @var16 = global i16 0
36 %old = atomicrmw add i16* @var16, i16 %offset acquire
39 ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16
40 ; CHECK: movt r[[ADDR]], :upper16:var16
132 %old = atomicrmw sub i16* @var16, i16 %offset release
135 ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16
136 ; CHECK: movt r[[ADDR]], :upper16:var16
228 %old = atomicrmw and i16* @var16, i16 %offset monotonic
231 ; CHECK: movw r[[ADDR:[0-9]+]], :lower16:var16
232 ; CHECK: movt r[[ADDR]], :upper16:var16
[all …]
/external/llvm/test/CodeGen/PowerPC/
Dfloat-asmprint.ll11 @var16 = global half -0.0, align 2
31 ; CHECK: var16:
/external/llvm-project/llvm/test/CodeGen/PowerPC/
Dfloat-asmprint.ll11 @var16 = global half -0.0, align 2
31 ; CHECK: var16:
/external/llvm/test/CodeGen/X86/
Dfloat-asmprint.ll11 @var16 = global half -0.0, align 2
40 ; CHECK: var16:
Dbswap.ll80 @var16 = global i16 0
94 %init = load i16, i16* @var16
143 %init = load i16, i16* @var16
/external/llvm-project/llvm/test/CodeGen/X86/
Dfloat-asmprint.ll11 @var16 = global half -0.0, align 2
40 ; CHECK: var16:
Dpr38185.ll54 %var16 = and i32 %var15, 63
55 %var17 = and i32 %var13, %var16
Dbswap.ll149 @var16 = global i16 0
158 ; CHECK-NEXT: movzwl var16, %eax
174 %init = load i16, i16* @var16
219 ; CHECK-NEXT: movzwl var16, %eax
231 %init = load i16, i16* @var16
/external/llvm-project/polly/test/ScopInfo/
Dnonaffine-buildMemoryAccess.ll42 %var16 = load i32, i32* %var1
43 %var17 = add i32 %var15, %var16

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