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Searched refs:imm12 (Results 1 – 8 of 8) sorted by relevance

/art/dex2oat/linker/riscv64/
Drelative_patcher_riscv64.cc86 uint32_t imm12 = disp & 0xfffu; // The instruction shall sign-extend this immediate. in PatchPcRelativeReference() local
87 insn = (insn & ~(0xfffu << 20)) | (imm12 << 20); in PatchPcRelativeReference()
Drelative_patcher_riscv64_test.cc88 uint32_t imm12 = offset & 0xfffu; in GenNopsAndAuipcAndUse() local
92 use_insn |= imm12 << 20; // Update `imm12` in `use_insn`. in GenNopsAndAuipcAndUse()
/art/disassembler/
Ddisassembler_arm.cc81 uint32_t imm12 = reinterpret_cast<const uint16_t*>(address)[1] & 0xfffu; in operator <<() local
83 options_->thread_offset_name_function_(os(), imm12); in operator <<()
Ddisassembler_riscv64.cc96 uint32_t imm12 = (insn32 >> 20); in Decode32Imm12() local
97 return static_cast<int32_t>(imm12) - static_cast<int32_t>(sign << 12); // Sign-extend. in Decode32Imm12()
413 int32_t imm12 = Decode32Imm12(insn32); in Print32Jalr() local
415 if (rd == Zero && rs1 == RA && imm12 == 0) { in Print32Jalr()
417 } else if (rd == Zero && imm12 == 0) { in Print32Jalr()
419 } else if (rd == RA && imm12 == 0) { in Print32Jalr()
426 if (imm12 == 0) { in Print32Jalr()
429 os_ << imm12 << "(" << XRegName(rs1) << ")"; in Print32Jalr()
/art/dex2oat/linker/arm64/
Drelative_patcher_arm64.cc306 uint32_t imm12 = (disp & 0xfffu) >> shift; in PatchPcRelativeReference() local
307 insn = (insn & ~(0xfffu << 10)) | (imm12 << 10); in PatchPcRelativeReference()
/art/compiler/utils/riscv64/
Dassembler_riscv64.h289 void Addi(XRegister rd, XRegister rs1, int32_t imm12);
290 void Slti(XRegister rd, XRegister rs1, int32_t imm12);
291 void Sltiu(XRegister rd, XRegister rs1, int32_t imm12);
292 void Xori(XRegister rd, XRegister rs1, int32_t imm12);
293 void Ori(XRegister rd, XRegister rs1, int32_t imm12);
294 void Andi(XRegister rd, XRegister rs1, int32_t imm12);
312 void Addiw(XRegister rd, XRegister rs1, int32_t imm12);
2332 void EmitI(int32_t imm12, Reg1 rs1, uint32_t funct3, Reg2 rd, uint32_t opcode) { in EmitI() argument
2333 DCHECK(IsInt<12>(imm12)) << imm12; in EmitI()
2338 uint32_t encoding = static_cast<uint32_t>(imm12) << 20 | static_cast<uint32_t>(rs1) << 15 | in EmitI()
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Dassembler_riscv64.cc305 void Riscv64Assembler::Addi(XRegister rd, XRegister rs1, int32_t imm12) { in Addi() argument
308 if (rs1 == Zero && IsInt<6>(imm12)) { in Addi()
309 CLi(rd, imm12); in Addi()
311 } else if (imm12 != 0) { in Addi()
315 if (IsInt<6>(imm12)) { in Addi()
316 CAddi(rd, imm12); in Addi()
318 } else if (rd == SP && IsInt<10>(imm12) && IsAligned<16>(imm12)) { in Addi()
319 CAddi16Sp(imm12); in Addi()
322 } else if (IsShortReg(rd) && rs1 == SP && IsUint<10>(imm12) && IsAligned<4>(imm12)) { in Addi()
323 CAddi4Spn(rd, imm12); in Addi()
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/art/compiler/optimizing/
Dcode_generator_riscv64.cc153 int32_t imm12 = dchecked_integral_cast<int32_t>(bits0_11) - in SplitJitAddress() local
155 return {base_address, imm12}; in SplitJitAddress()
268 CompileOptimizedSlowPathRISCV64(HSuspendCheck* suspend_check, XRegister base, int32_t imm12) in CompileOptimizedSlowPathRISCV64() argument
271 imm12_(imm12) {} in CompileOptimizedSlowPathRISCV64()
5911 auto [base_address, imm12] = SplitJitAddress(address); in MaybeIncrementHotness()
5917 new (GetScopedAllocator()) CompileOptimizedSlowPathRISCV64(suspend_check, tmp, imm12); in MaybeIncrementHotness()
5919 __ Lhu(counter, tmp, imm12); in MaybeIncrementHotness()
5922 __ Sh(counter, tmp, imm12); in MaybeIncrementHotness()