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Searched refs:reg (Results 1 – 25 of 166) sorted by relevance

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/art/compiler/utils/x86_64/
Dmanaged_register_x86_64_test.cc26 X86_64ManagedRegister reg = ManagedRegister::NoRegister().AsX86(); in TEST() local
27 EXPECT_TRUE(reg.IsNoRegister()); in TEST()
28 EXPECT_TRUE(!reg.Overlaps(reg)); in TEST()
32 X86_64ManagedRegister reg = X86_64ManagedRegister::FromCpuRegister(RAX); in TEST() local
33 EXPECT_TRUE(!reg.IsNoRegister()); in TEST()
34 EXPECT_TRUE(reg.IsCpuRegister()); in TEST()
35 EXPECT_TRUE(!reg.IsXmmRegister()); in TEST()
36 EXPECT_TRUE(!reg.IsX87Register()); in TEST()
37 EXPECT_TRUE(!reg.IsRegisterPair()); in TEST()
38 EXPECT_EQ(RAX, reg.AsCpuRegister()); in TEST()
[all …]
Dassembler_x86_64.h130 bool IsRegister(CpuRegister reg) const { in IsRegister() argument
132 && ((encoding_[0] & 0x07) == reg.LowBits()) // Register codes match. in IsRegister()
133 && (reg.NeedsRex() == ((rex_ & 1) != 0)); // REX.000B bits match. in IsRegister()
196 explicit Operand(CpuRegister reg) : rex_(0), length_(0), fixup_(nullptr) { SetModRM(3, reg); } in Operand() argument
433 void call(CpuRegister reg);
437 void pushq(CpuRegister reg);
441 void popq(CpuRegister reg);
739 void psllw(XmmRegister reg, const Immediate& shift_count);
740 void pslld(XmmRegister reg, const Immediate& shift_count);
741 void psllq(XmmRegister reg, const Immediate& shift_count);
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/art/compiler/utils/x86/
Dmanaged_register_x86_test.cc27 X86ManagedRegister reg = ManagedRegister::NoRegister().AsX86(); in TEST() local
28 EXPECT_TRUE(reg.IsNoRegister()); in TEST()
29 EXPECT_TRUE(!reg.Overlaps(reg)); in TEST()
33 X86ManagedRegister reg = X86ManagedRegister::FromCpuRegister(EAX); in TEST() local
34 EXPECT_TRUE(!reg.IsNoRegister()); in TEST()
35 EXPECT_TRUE(reg.IsCpuRegister()); in TEST()
36 EXPECT_TRUE(!reg.IsXmmRegister()); in TEST()
37 EXPECT_TRUE(!reg.IsX87Register()); in TEST()
38 EXPECT_TRUE(!reg.IsRegisterPair()); in TEST()
39 EXPECT_EQ(EAX, reg.AsCpuRegister()); in TEST()
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/art/compiler/utils/arm/
Dmanaged_register_arm_test.cc26 ArmManagedRegister reg = ManagedRegister::NoRegister().AsArm(); in TEST() local
27 EXPECT_TRUE(reg.IsNoRegister()); in TEST()
28 EXPECT_TRUE(!reg.Overlaps(reg)); in TEST()
32 ArmManagedRegister reg = ArmManagedRegister::FromCoreRegister(R0); in TEST() local
33 EXPECT_TRUE(!reg.IsNoRegister()); in TEST()
34 EXPECT_TRUE(reg.IsCoreRegister()); in TEST()
35 EXPECT_TRUE(!reg.IsSRegister()); in TEST()
36 EXPECT_TRUE(!reg.IsDRegister()); in TEST()
37 EXPECT_TRUE(!reg.IsRegisterPair()); in TEST()
38 EXPECT_EQ(R0, reg.AsCoreRegister()); in TEST()
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/art/compiler/utils/riscv64/
Dmanaged_register_riscv64_test.cc26 Riscv64ManagedRegister reg = ManagedRegister::NoRegister().AsRiscv64(); in TEST() local
27 EXPECT_TRUE(reg.IsNoRegister()); in TEST()
31 Riscv64ManagedRegister reg = Riscv64ManagedRegister::FromXRegister(Zero); in TEST() local
32 EXPECT_FALSE(reg.IsNoRegister()); in TEST()
33 EXPECT_TRUE(reg.IsXRegister()); in TEST()
34 EXPECT_FALSE(reg.IsFRegister()); in TEST()
35 EXPECT_EQ(Zero, reg.AsXRegister()); in TEST()
37 reg = Riscv64ManagedRegister::FromXRegister(RA); in TEST()
38 EXPECT_FALSE(reg.IsNoRegister()); in TEST()
39 EXPECT_TRUE(reg.IsXRegister()); in TEST()
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Dmanaged_register_riscv64.h115 Riscv64ManagedRegister reg(reg_id); in FromRegId()
116 CHECK(reg.IsValidManagedRegister()); in FromRegId()
117 return reg; in FromRegId()
121 std::ostream& operator<<(std::ostream& os, const Riscv64ManagedRegister& reg);
126 riscv64::Riscv64ManagedRegister reg(id_); in AsRiscv64()
127 CHECK(reg.IsNoRegister() || reg.IsValidManagedRegister()); in AsRiscv64()
128 return reg; in AsRiscv64()
/art/compiler/debug/
Delf_debug_frame_writer.h50 for (int reg = 0; reg < 13; reg++) { in WriteCIE() local
51 if (reg < 4 || reg == 12) { in WriteCIE()
52 opcodes.Undefined(Reg::ArmCore(reg)); in WriteCIE()
54 opcodes.SameValue(Reg::ArmCore(reg)); in WriteCIE()
58 for (int reg = 0; reg < 32; reg++) { in WriteCIE() local
59 if (reg < 16) { in WriteCIE()
60 opcodes.Undefined(Reg::ArmFp(reg)); in WriteCIE()
62 opcodes.SameValue(Reg::ArmFp(reg)); in WriteCIE()
73 for (int reg = 0; reg < 30; reg++) { in WriteCIE() local
74 if (reg < 8 || reg == 16 || reg == 17) { in WriteCIE()
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/art/compiler/utils/arm64/
Dmanaged_register_arm64_test.cc28 Arm64ManagedRegister reg = ManagedRegister::NoRegister().AsArm64(); in TEST() local
29 EXPECT_TRUE(reg.IsNoRegister()); in TEST()
30 EXPECT_TRUE(!reg.Overlaps(reg)); in TEST()
35 Arm64ManagedRegister reg = Arm64ManagedRegister::FromXRegister(X0); in TEST() local
37 EXPECT_TRUE(!reg.IsNoRegister()); in TEST()
38 EXPECT_TRUE(reg.IsXRegister()); in TEST()
39 EXPECT_TRUE(!reg.IsWRegister()); in TEST()
40 EXPECT_TRUE(!reg.IsDRegister()); in TEST()
41 EXPECT_TRUE(!reg.IsSRegister()); in TEST()
42 EXPECT_TRUE(reg.Overlaps(wreg)); in TEST()
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/art/runtime/arch/arm/
Dcontext_arm.h57 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR() argument
58 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters)); in IsAccessibleGPR()
59 return gprs_[reg] != nullptr; in IsAccessibleGPR()
62 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress() argument
63 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters)); in GetGPRAddress()
64 return gprs_[reg]; in GetGPRAddress()
67 uintptr_t GetGPR(uint32_t reg) override { in GetGPR() argument
68 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters)); in GetGPR()
69 DCHECK(IsAccessibleGPR(reg)); in GetGPR()
70 return *gprs_[reg]; in GetGPR()
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Dasm_support_arm.S50 .macro CFI_DEF_CFA_BREG_PLUS_UCONST reg, offset, size
58 CFI_DEF_CFA_BREG_PLUS_UCONST_1_1(\reg, \offset, \size)
60 CFI_DEF_CFA_BREG_PLUS_UCONST_1_2(\reg, \offset, \size)
73 .macro CFI_RESTORE_STATE_AND_DEF_CFA reg, offset
75 .cfi_def_cfa \reg, \offset
165 .macro CONDITIONAL_CBZ reg, reg_if, dest
166 .ifc \reg, \reg_if
167 cbz \reg, \dest
171 .macro CONDITIONAL_CMPBZ reg, reg_if, dest
172 .ifc \reg, \reg_if
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/art/runtime/arch/arm64/
Dcontext_arm64.h57 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR() argument
58 DCHECK_LT(reg, arraysize(gprs_)); in IsAccessibleGPR()
59 return gprs_[reg] != nullptr; in IsAccessibleGPR()
62 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress() argument
63 DCHECK_LT(reg, arraysize(gprs_)); in GetGPRAddress()
64 return gprs_[reg]; in GetGPRAddress()
67 uintptr_t GetGPR(uint32_t reg) override { in GetGPR() argument
69 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfXRegisters)); in GetGPR()
70 DCHECK(IsAccessibleGPR(reg)); in GetGPR()
71 return *gprs_[reg]; in GetGPR()
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/art/runtime/arch/x86_64/
Dcontext_x86_64.h56 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR() argument
57 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters)); in IsAccessibleGPR()
58 return gprs_[reg] != nullptr; in IsAccessibleGPR()
61 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress() argument
62 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters)); in GetGPRAddress()
63 return gprs_[reg]; in GetGPRAddress()
66 uintptr_t GetGPR(uint32_t reg) override { in GetGPR() argument
67 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters)); in GetGPR()
68 DCHECK(IsAccessibleGPR(reg)); in GetGPR()
69 return *gprs_[reg]; in GetGPR()
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Dasm_support_x86_64.S76 #define CFI_DEF_CFA(reg,size) .cfi_def_cfa reg,size argument
77 #define CFI_DEF_CFA_REGISTER(reg) .cfi_def_cfa_register reg argument
78 #define CFI_RESTORE(reg) .cfi_restore reg argument
79 #define CFI_REL_OFFSET(reg,size) .cfi_rel_offset reg,size argument
86 MACRO2(CFI_RESTORE_STATE_AND_DEF_CFA, reg, off)
88 .cfi_def_cfa \reg,\off
96 #define CFI_DEF_CFA(reg,size) argument
97 #define CFI_DEF_CFA_REGISTER(reg) argument
98 #define CFI_RESTORE(reg) argument
99 #define CFI_REL_OFFSET(reg,size) argument
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/art/runtime/arch/riscv64/
Dcontext_riscv64.h49 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR() argument
50 DCHECK_LT(reg, arraysize(gprs_)); in IsAccessibleGPR()
51 return gprs_[reg] != nullptr; in IsAccessibleGPR()
54 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress() argument
55 DCHECK_LT(reg, arraysize(gprs_)); in GetGPRAddress()
56 return gprs_[reg]; in GetGPRAddress()
59 uintptr_t GetGPR(uint32_t reg) override { in GetGPR() argument
61 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfXRegisters)); in GetGPR()
62 DCHECK(IsAccessibleGPR(reg)); in GetGPR()
63 return *gprs_[reg]; in GetGPR()
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Dasm_support_riscv64.S59 .macro CFI_RESTORE_STATE_AND_DEF_CFA reg, offset
61 .cfi_def_cfa \reg, \offset
76 .macro CFI_DEF_CFA_BREG_PLUS_UCONST reg, offset, size
84 CFI_DEF_CFA_BREG_PLUS_UCONST_1_1(\reg, \offset, \size)
86 CFI_DEF_CFA_BREG_PLUS_UCONST_1_2(\reg, \offset, \size)
123 .macro SAVE_GPR_BASE base, reg, offset
124 sd \reg, (\offset)(\base)
125 .cfi_rel_offset \reg, (\offset)
129 .macro SAVE_GPR reg, offset
130 SAVE_GPR_BASE sp, \reg, \offset
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/art/runtime/arch/x86/
Dcontext_x86.h56 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR() argument
57 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters)); in IsAccessibleGPR()
58 return gprs_[reg] != nullptr; in IsAccessibleGPR()
61 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress() argument
62 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters)); in GetGPRAddress()
63 return gprs_[reg]; in GetGPRAddress()
66 uintptr_t GetGPR(uint32_t reg) override { in GetGPR() argument
67 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters)); in GetGPR()
68 DCHECK(IsAccessibleGPR(reg)); in GetGPR()
69 return *gprs_[reg]; in GetGPR()
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Dasm_support_x86.S77 #define CFI_DEF_CFA(reg,size) .cfi_def_cfa reg,size argument
78 #define CFI_DEF_CFA_REGISTER(reg) .cfi_def_cfa_register reg argument
79 #define CFI_RESTORE(reg) .cfi_restore reg argument
80 #define CFI_REL_OFFSET(reg,size) .cfi_rel_offset reg,size argument
87 MACRO2(CFI_RESTORE_STATE_AND_DEF_CFA, reg, off)
89 .cfi_def_cfa \reg,\off
98 #define CFI_DEF_CFA(reg,size) argument
99 #define CFI_DEF_CFA_REGISTER(reg) argument
100 #define CFI_RESTORE(reg) argument
101 #define CFI_REL_OFFSET(reg,size) argument
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/art/runtime/
Ddex_register_location.cc25 std::ostream& operator<<(std::ostream& stream, const DexRegisterLocation& reg) { in operator <<() argument
27 switch (reg.GetKind()) { in operator <<()
33 return stream << "sp+" << reg.GetValue(); in operator <<()
35 return stream << "r" << reg.GetValue(); in operator <<()
37 return stream << "r" << reg.GetValue() << "/hi"; in operator <<()
39 return stream << "f" << reg.GetValue(); in operator <<()
41 return stream << "f" << reg.GetValue() << "/hi"; in operator <<()
43 return stream << "#" << reg.GetValue(); in operator <<()
45 return stream << "DexRegisterLocation(" << static_cast<uint32_t>(reg.GetKind()) in operator <<()
46 << "," << reg.GetValue() << ")"; in operator <<()
/art/test/404-optimizing-allocator/src/
DMain.java23 expectEquals(4, $opt$reg$TestLostCopy()); in main()
24 expectEquals(-10, $opt$reg$TestTwoLive()); in main()
25 expectEquals(-20, $opt$reg$TestThreeLive()); in main()
26 expectEquals(5, $opt$reg$TestFourLive()); in main()
27 expectEquals(10, $opt$reg$TestMultipleLive()); in main()
28 expectEquals(1, $opt$reg$TestWithBreakAndContinue()); in main()
29 expectEquals(-15, $opt$reg$testSpillInIf(5, 6, 7)); in main()
30 expectEquals(-567, $opt$reg$TestAgressiveLive1(1, 2, 3, 4, 5, 6, 7)); in main()
31 expectEquals(-77, $opt$reg$TestAgressiveLive2(1, 2, 3, 4, 5, 6, 7)); in main()
34 public static int $opt$reg$TestLostCopy() { in $opt$reg$TestLostCopy()
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/art/libelffile/dwarf/
Ddebug_frame_opcode_writer.h73 void ALWAYS_INLINE RelOffset(Reg reg, int offset) { in RelOffset() argument
74 Offset(reg, offset - current_cfa_offset_); in RelOffset()
119 void ALWAYS_INLINE Offset(Reg reg, int offset) { in Offset() argument
124 if (0 <= reg.num() && reg.num() <= 0x3F) { in Offset()
125 this->PushUint8(DW_CFA_offset | reg.num()); in Offset()
129 this->PushUleb128(reg.num()); in Offset()
135 this->PushUleb128(reg.num()); in Offset()
141 void ALWAYS_INLINE Restore(Reg reg) { in Restore() argument
144 if (0 <= reg.num() && reg.num() <= 0x3F) { in Restore()
145 this->PushUint8(DW_CFA_restore | reg.num()); in Restore()
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/art/runtime/interpreter/mterp/riscv64/
Dmain.S147 .macro TEST_IF_MARKING reg, label
148 lb \reg, THREAD_IS_GC_MARKING_OFFSET(xSELF)
149 bnez \reg, \label
172 .macro FETCH reg, count, signed=0, width=16, byte=0
175 lb \reg, (\count*2 + \byte)(xPC)
177 lbu \reg, (\count*2 + \byte)(xPC)
181 lh \reg, (\count*2)(xPC)
183 lhu \reg, (\count*2)(xPC)
187 lw \reg, (\count*2)(xPC)
189 lwu \reg, (\count*2)(xPC)
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/art/compiler/optimizing/
Dcritical_native_abi_fixup_arm.cc29 size_t reg = 0u; in FixUpArguments() local
33 size_t next_reg = reg + 1u; in FixUpArguments()
35 reg = RoundUp(reg, 2u); in FixUpArguments()
36 next_reg = reg + 2u; in FixUpArguments()
38 if (reg == 4u) { in FixUpArguments()
44 reg = next_reg; in FixUpArguments()
Dregister_allocator_linear_scan.cc38 static int GetHighForLowRegister(int reg) { return reg + 1; } in GetHighForLowRegister() argument
39 static bool IsLowRegister(int reg) { return (reg & 1) == 0; } in IsLowRegister() argument
133 int reg = location.reg(); in BlockRegister() local
137 if ((registers_blocked_for_call & (1u << reg)) != 0u) { in BlockRegister()
144 ? physical_core_register_intervals_[reg] in BlockRegister()
145 : physical_fp_register_intervals_[reg]; in BlockRegister()
150 interval = LiveInterval::MakeFixedInterval(allocator_, reg, type); in BlockRegister()
152 physical_core_register_intervals_[reg] = interval; in BlockRegister()
154 physical_fp_register_intervals_[reg] = interval; in BlockRegister()
157 DCHECK(interval->GetRegister() == reg); in BlockRegister()
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/art/runtime/interpreter/
Dcfi_asm_support.h48 #define CFI_DEF_CFA_BREG_PLUS_UCONST_1_1(reg, offset, size) .cfi_escape \ argument
50 0x92 /* bregx */, reg, (offset & 0x7F), \
54 #define CFI_DEF_CFA_BREG_PLUS_UCONST_1_2(reg, offset, size) .cfi_escape \ argument
56 0x92 /* bregx */, reg, (offset & 0x7F), \
80 #define CFI_DEF_CFA_BREG_PLUS_UCONST_1_1(reg, offset, size) argument
81 #define CFI_DEF_CFA_BREG_PLUS_UCONST_1_2(reg, offset, size) argument
/art/runtime/arch/
Dcontext.h64 virtual bool IsAccessibleGPR(uint32_t reg) = 0;
67 virtual uintptr_t* GetGPRAddress(uint32_t reg) = 0;
71 virtual uintptr_t GetGPR(uint32_t reg) = 0;
75 virtual void SetGPR(uint32_t reg, uintptr_t value) = 0;
78 virtual bool IsAccessibleFPR(uint32_t reg) = 0;
82 virtual uintptr_t GetFPR(uint32_t reg) = 0;
86 virtual void SetFPR(uint32_t reg, uintptr_t value) = 0;

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