1686   switch (static_cast<ExtendedMIROpcode>(mir->dalvikInsn.opcode)) {  in GenMachineSpecificExtendedMethodMIR()
1744   int num_vector_reg = mir->dalvikInsn.vA;  in ReserveVectorRegisters()
1787   int type_size = mir->dalvikInsn.vB;  in GenConst128()
1790   RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vA);  in GenConst128()
1791   uint32_t *args = mir->dalvikInsn.arg;  in GenConst128()
1830   DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);  in GenMoveVector()
1831   RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vA);  in GenMoveVector()
1832   RegStorage rs_src = RegStorage::Solo128(mir->dalvikInsn.vB);  in GenMoveVector()
1838   RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);  in GenMultiplyVectorSignedByte()
1839   RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB);  in GenMultiplyVectorSignedByte()
1879   DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);  in GenMultiplyVector()
1880   OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);  in GenMultiplyVector()
1881   RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);  in GenMultiplyVector()
1882   RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB);  in GenMultiplyVector()
1909   DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);  in GenAddVector()
1910   OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);  in GenAddVector()
1911   RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);  in GenAddVector()
1912   RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB);  in GenAddVector()
1940   DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);  in GenSubtractVector()
1941   OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);  in GenSubtractVector()
1942   RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);  in GenSubtractVector()
1943   RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB);  in GenSubtractVector()
1971   RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);  in GenShiftByteVector()
1975   int imm = mir->dalvikInsn.vB;  in GenShiftByteVector()
1977   switch (static_cast<ExtendedMIROpcode>(mir->dalvikInsn.opcode)) {  in GenShiftByteVector()
2020   DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);  in GenShiftLeftVector()
2021   OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);  in GenShiftLeftVector()
2022   RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);  in GenShiftLeftVector()
2023   int imm = mir->dalvikInsn.vB;  in GenShiftLeftVector()
2048   DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);  in GenSignedShiftRightVector()
2049   OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);  in GenSignedShiftRightVector()
2050   RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);  in GenSignedShiftRightVector()
2051   int imm = mir->dalvikInsn.vB;  in GenSignedShiftRightVector()
2073   DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);  in GenUnsignedShiftRightVector()
2074   OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);  in GenUnsignedShiftRightVector()
2075   RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);  in GenUnsignedShiftRightVector()
2076   int imm = mir->dalvikInsn.vB;  in GenUnsignedShiftRightVector()
2102   DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);  in GenAndVector()
2103   RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);  in GenAndVector()
2104   RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB);  in GenAndVector()
2110   DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);  in GenOrVector()
2111   RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);  in GenOrVector()
2112   RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB);  in GenOrVector()
2118   DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);  in GenXorVector()
2119   RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA);  in GenXorVector()
2120   RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB);  in GenXorVector()
2132   const_mirp->dalvikInsn.opcode = static_cast<Instruction::Code>(kMirOpConstVector);  in MaskVectorRegister()
2133   const_mirp->dalvikInsn.arg[0] = m0;  in MaskVectorRegister()
2134   const_mirp->dalvikInsn.arg[1] = m1;  in MaskVectorRegister()
2135   const_mirp->dalvikInsn.arg[2] = m2;  in MaskVectorRegister()
2136   const_mirp->dalvikInsn.arg[3] = m3;  in MaskVectorRegister()
2143   OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);  in GenAddReduceVector()
2144   RegStorage rs_src1 = RegStorage::Solo128(mir->dalvikInsn.vB);  in GenAddReduceVector()
2148   int vec_bytes = (mir->dalvikInsn.vC & 0xFFFF) / 8;  in GenAddReduceVector()
2236   OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);  in GenReduceVector()
2238   RegStorage rs_src1 = RegStorage::Solo128(mir->dalvikInsn.vB);  in GenReduceVector()
2239   int extract_index = mir->dalvikInsn.arg[0];  in GenReduceVector()
2276   DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U);  in GenSetVector()
2277   OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16);  in GenSetVector()
2278   RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vA);  in GenSetVector()
2349   int *args = reinterpret_cast<int*>(mir->dalvikInsn.arg);  in ScanVectorLiteral()
2361   int *args = reinterpret_cast<int*>(mir->dalvikInsn.arg);  in AddVectorLiteral()