Lines Matching refs:mir
1685 void X86Mir2Lir::GenMachineSpecificExtendedMethodMIR(BasicBlock* bb, MIR* mir) { in GenMachineSpecificExtendedMethodMIR() argument
1686 switch (static_cast<ExtendedMIROpcode>(mir->dalvikInsn.opcode)) { in GenMachineSpecificExtendedMethodMIR()
1688 ReserveVectorRegisters(mir); in GenMachineSpecificExtendedMethodMIR()
1694 GenConst128(bb, mir); in GenMachineSpecificExtendedMethodMIR()
1697 GenMoveVector(bb, mir); in GenMachineSpecificExtendedMethodMIR()
1700 GenMultiplyVector(bb, mir); in GenMachineSpecificExtendedMethodMIR()
1703 GenAddVector(bb, mir); in GenMachineSpecificExtendedMethodMIR()
1706 GenSubtractVector(bb, mir); in GenMachineSpecificExtendedMethodMIR()
1709 GenShiftLeftVector(bb, mir); in GenMachineSpecificExtendedMethodMIR()
1712 GenSignedShiftRightVector(bb, mir); in GenMachineSpecificExtendedMethodMIR()
1715 GenUnsignedShiftRightVector(bb, mir); in GenMachineSpecificExtendedMethodMIR()
1718 GenAndVector(bb, mir); in GenMachineSpecificExtendedMethodMIR()
1721 GenOrVector(bb, mir); in GenMachineSpecificExtendedMethodMIR()
1724 GenXorVector(bb, mir); in GenMachineSpecificExtendedMethodMIR()
1727 GenAddReduceVector(bb, mir); in GenMachineSpecificExtendedMethodMIR()
1730 GenReduceVector(bb, mir); in GenMachineSpecificExtendedMethodMIR()
1733 GenSetVector(bb, mir); in GenMachineSpecificExtendedMethodMIR()
1740 void X86Mir2Lir::ReserveVectorRegisters(MIR* mir) { in ReserveVectorRegisters() argument
1744 int num_vector_reg = mir->dalvikInsn.vA; in ReserveVectorRegisters()
1785 void X86Mir2Lir::GenConst128(BasicBlock* bb, MIR* mir) { in GenConst128() argument
1787 int type_size = mir->dalvikInsn.vB; in GenConst128()
1790 RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vA); in GenConst128()
1791 uint32_t *args = mir->dalvikInsn.arg; in GenConst128()
1800 AppendOpcodeWithConst(kX86MovupsRM, reg, mir); in GenConst128()
1803 void X86Mir2Lir::AppendOpcodeWithConst(X86OpCode opcode, int reg, MIR* mir) { in AppendOpcodeWithConst() argument
1805 LIR *data_target = ScanVectorLiteral(mir); in AppendOpcodeWithConst()
1807 data_target = AddVectorLiteral(mir); in AppendOpcodeWithConst()
1828 void X86Mir2Lir::GenMoveVector(BasicBlock *bb, MIR *mir) { in GenMoveVector() argument
1830 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); in GenMoveVector()
1831 RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vA); in GenMoveVector()
1832 RegStorage rs_src = RegStorage::Solo128(mir->dalvikInsn.vB); in GenMoveVector()
1836 void X86Mir2Lir::GenMultiplyVectorSignedByte(BasicBlock *bb, MIR *mir) { in GenMultiplyVectorSignedByte() argument
1838 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); in GenMultiplyVectorSignedByte()
1839 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB); in GenMultiplyVectorSignedByte()
1878 void X86Mir2Lir::GenMultiplyVector(BasicBlock *bb, MIR *mir) { in GenMultiplyVector() argument
1879 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); in GenMultiplyVector()
1880 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); in GenMultiplyVector()
1881 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); in GenMultiplyVector()
1882 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB); in GenMultiplyVector()
1899 GenMultiplyVectorSignedByte(bb, mir); in GenMultiplyVector()
1908 void X86Mir2Lir::GenAddVector(BasicBlock *bb, MIR *mir) { in GenAddVector() argument
1909 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); in GenAddVector()
1910 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); in GenAddVector()
1911 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); in GenAddVector()
1912 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB); in GenAddVector()
1939 void X86Mir2Lir::GenSubtractVector(BasicBlock *bb, MIR *mir) { in GenSubtractVector() argument
1940 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); in GenSubtractVector()
1941 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); in GenSubtractVector()
1942 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); in GenSubtractVector()
1943 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB); in GenSubtractVector()
1970 void X86Mir2Lir::GenShiftByteVector(BasicBlock *bb, MIR *mir) { in GenShiftByteVector() argument
1971 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); in GenShiftByteVector()
1975 int imm = mir->dalvikInsn.vB; in GenShiftByteVector()
1977 switch (static_cast<ExtendedMIROpcode>(mir->dalvikInsn.opcode)) { in GenShiftByteVector()
2019 void X86Mir2Lir::GenShiftLeftVector(BasicBlock *bb, MIR *mir) { in GenShiftLeftVector() argument
2020 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); in GenShiftLeftVector()
2021 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); in GenShiftLeftVector()
2022 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); in GenShiftLeftVector()
2023 int imm = mir->dalvikInsn.vB; in GenShiftLeftVector()
2038 GenShiftByteVector(bb, mir); in GenShiftLeftVector()
2047 void X86Mir2Lir::GenSignedShiftRightVector(BasicBlock *bb, MIR *mir) { in GenSignedShiftRightVector() argument
2048 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); in GenSignedShiftRightVector()
2049 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); in GenSignedShiftRightVector()
2050 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); in GenSignedShiftRightVector()
2051 int imm = mir->dalvikInsn.vB; in GenSignedShiftRightVector()
2063 GenShiftByteVector(bb, mir); in GenSignedShiftRightVector()
2072 void X86Mir2Lir::GenUnsignedShiftRightVector(BasicBlock *bb, MIR *mir) { in GenUnsignedShiftRightVector() argument
2073 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); in GenUnsignedShiftRightVector()
2074 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); in GenUnsignedShiftRightVector()
2075 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); in GenUnsignedShiftRightVector()
2076 int imm = mir->dalvikInsn.vB; in GenUnsignedShiftRightVector()
2091 GenShiftByteVector(bb, mir); in GenUnsignedShiftRightVector()
2100 void X86Mir2Lir::GenAndVector(BasicBlock *bb, MIR *mir) { in GenAndVector() argument
2102 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); in GenAndVector()
2103 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); in GenAndVector()
2104 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB); in GenAndVector()
2108 void X86Mir2Lir::GenOrVector(BasicBlock *bb, MIR *mir) { in GenOrVector() argument
2110 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); in GenOrVector()
2111 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); in GenOrVector()
2112 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB); in GenOrVector()
2116 void X86Mir2Lir::GenXorVector(BasicBlock *bb, MIR *mir) { in GenXorVector() argument
2118 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); in GenXorVector()
2119 RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); in GenXorVector()
2120 RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB); in GenXorVector()
2142 void X86Mir2Lir::GenAddReduceVector(BasicBlock *bb, MIR *mir) { in GenAddReduceVector() argument
2143 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); in GenAddReduceVector()
2144 RegStorage rs_src1 = RegStorage::Solo128(mir->dalvikInsn.vB); in GenAddReduceVector()
2145 RegLocation rl_dest = mir_graph_->GetDest(mir); in GenAddReduceVector()
2148 int vec_bytes = (mir->dalvikInsn.vC & 0xFFFF) / 8; in GenAddReduceVector()
2235 void X86Mir2Lir::GenReduceVector(BasicBlock *bb, MIR *mir) { in GenReduceVector() argument
2236 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); in GenReduceVector()
2237 RegLocation rl_dest = mir_graph_->GetDest(mir); in GenReduceVector()
2238 RegStorage rs_src1 = RegStorage::Solo128(mir->dalvikInsn.vB); in GenReduceVector()
2239 int extract_index = mir->dalvikInsn.arg[0]; in GenReduceVector()
2275 void X86Mir2Lir::GenSetVector(BasicBlock *bb, MIR *mir) { in GenSetVector() argument
2276 DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); in GenSetVector()
2277 OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); in GenSetVector()
2278 RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vA); in GenSetVector()
2317 RegLocation rl_src = mir_graph_->GetSrc(mir, 0); in GenSetVector()
2348 LIR *X86Mir2Lir::ScanVectorLiteral(MIR *mir) { in ScanVectorLiteral() argument
2349 int *args = reinterpret_cast<int*>(mir->dalvikInsn.arg); in ScanVectorLiteral()
2359 LIR *X86Mir2Lir::AddVectorLiteral(MIR *mir) { in AddVectorLiteral() argument
2361 int *args = reinterpret_cast<int*>(mir->dalvikInsn.arg); in AddVectorLiteral()