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Searched defs:reg (Results 1 – 25 of 84) sorted by relevance

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/art/compiler/utils/x86_64/
Dmanaged_register_x86_64_test.cc25 X86_64ManagedRegister reg = ManagedRegister::NoRegister().AsX86(); in TEST() local
31 X86_64ManagedRegister reg = X86_64ManagedRegister::FromCpuRegister(RAX); in TEST() local
65 X86_64ManagedRegister reg = X86_64ManagedRegister::FromXmmRegister(XMM0); in TEST() local
91 X86_64ManagedRegister reg = X86_64ManagedRegister::FromX87Register(ST0); in TEST() local
117 X86_64ManagedRegister reg = X86_64ManagedRegister::FromRegisterPair(EAX_EDX); in TEST() local
255 X86_64ManagedRegister reg = X86_64ManagedRegister::FromCpuRegister(RAX); in TEST() local
Dmanaged_register_x86_64.cc40 RegisterPair reg; // Used to verify that the enum is in sync. member
52 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg) { in operator <<()
109 std::ostream& operator<<(std::ostream& os, const X86_64ManagedRegister& reg) { in operator <<()
Dassembler_x86_64.h99 bool IsRegister(CpuRegister reg) const { in IsRegister()
149 explicit Operand(CpuRegister reg) : rex_(0), length_(0) { SetModRM(3, reg); } in Operand()
489 void LockCmpxchgl(const Address& address, CpuRegister reg) { in LockCmpxchgl()
673 inline void X86_64Assembler::EmitRegisterOperand(uint8_t rm, uint8_t reg) { in EmitRegisterOperand()
679 inline void X86_64Assembler::EmitXmmRegisterOperand(uint8_t rm, XmmRegister reg) { in EmitXmmRegisterOperand()
Dassembler_x86_64.cc27 std::ostream& operator<<(std::ostream& os, const CpuRegister& reg) { in operator <<()
31 std::ostream& operator<<(std::ostream& os, const XmmRegister& reg) { in operator <<()
35 std::ostream& operator<<(std::ostream& os, const X87Register& reg) { in operator <<()
39 void X86_64Assembler::call(CpuRegister reg) { in call()
62 void X86_64Assembler::pushq(CpuRegister reg) { in pushq()
90 void X86_64Assembler::popq(CpuRegister reg) { in popq()
833 void X86_64Assembler::xchgl(CpuRegister reg, const Address& address) { in xchgl()
841 void X86_64Assembler::cmpl(CpuRegister reg, const Immediate& imm) { in cmpl()
856 void X86_64Assembler::cmpl(CpuRegister reg, const Address& address) { in cmpl()
872 void X86_64Assembler::cmpq(CpuRegister reg, const Immediate& imm) { in cmpq()
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/art/compiler/utils/x86/
Dmanaged_register_x86_test.cc25 X86ManagedRegister reg = ManagedRegister::NoRegister().AsX86(); in TEST() local
31 X86ManagedRegister reg = X86ManagedRegister::FromCpuRegister(EAX); in TEST() local
65 X86ManagedRegister reg = X86ManagedRegister::FromXmmRegister(XMM0); in TEST() local
91 X86ManagedRegister reg = X86ManagedRegister::FromX87Register(ST0); in TEST() local
117 X86ManagedRegister reg = X86ManagedRegister::FromRegisterPair(EAX_EDX); in TEST() local
255 X86ManagedRegister reg = X86ManagedRegister::FromCpuRegister(EAX); in TEST() local
Dmanaged_register_x86.cc41 RegisterPair reg; // Used to verify that the enum is in sync. member
53 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg) { in operator <<()
110 std::ostream& operator<<(std::ostream& os, const X86ManagedRegister& reg) { in operator <<()
Dassembler_x86.h83 bool IsRegister(Register reg) const { in IsRegister()
121 explicit Operand(Register reg) { SetModRM(3, reg); } in Operand()
447 void LockCmpxchgl(const Address& address, Register reg) { in LockCmpxchgl()
603 inline void X86Assembler::EmitRegisterOperand(int rm, int reg) { in EmitRegisterOperand()
609 inline void X86Assembler::EmitXmmRegisterOperand(int rm, XmmRegister reg) { in EmitXmmRegisterOperand()
Dassembler_x86.cc27 std::ostream& operator<<(std::ostream& os, const XmmRegister& reg) { in operator <<()
31 std::ostream& operator<<(std::ostream& os, const X87Register& reg) { in operator <<()
35 void X86Assembler::call(Register reg) { in call()
67 void X86Assembler::pushl(Register reg) { in pushl()
92 void X86Assembler::popl(Register reg) { in popl()
748 void X86Assembler::xchgl(Register reg, const Address& address) { in xchgl()
755 void X86Assembler::cmpl(Register reg, const Immediate& imm) { in cmpl()
768 void X86Assembler::cmpl(Register reg, const Address& address) { in cmpl()
782 void X86Assembler::addl(Register reg, const Address& address) { in addl()
789 void X86Assembler::cmpl(const Address& address, Register reg) { in cmpl()
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/art/compiler/dex/quick/
Dralloc_util.cc85 for (const RegStorage& reg : core_regs) { in RegisterPool() local
90 for (const RegStorage& reg : core64_regs) { in RegisterPool() local
95 for (const RegStorage& reg : sp_regs) { in RegisterPool() local
100 for (const RegStorage& reg : dp_regs) { in RegisterPool() local
107 for (RegStorage reg : reserved_regs) { in RegisterPool() local
110 for (RegStorage reg : reserved64_regs) { in RegisterPool() local
115 for (RegStorage reg : core_temps) { in RegisterPool() local
118 for (RegStorage reg : core64_temps) { in RegisterPool() local
121 for (RegStorage reg : sp_temps) { in RegisterPool() local
124 for (RegStorage reg : dp_temps) { in RegisterPool() local
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/art/runtime/arch/x86/
Dcontext_x86.h47 uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE { in GetGPRAddress()
52 bool GetGPR(uint32_t reg, uintptr_t* val) OVERRIDE { in GetGPR()
65 bool GetFPR(uint32_t reg, uintptr_t* val) OVERRIDE { in GetFPR()
70 bool SetFPR(uint32_t reg, uintptr_t value) OVERRIDE { in SetFPR()
Dasm_support_x86.S80 #define CFI_DEF_CFA(reg,size) .cfi_def_cfa reg,size argument
81 #define CFI_DEF_CFA_REGISTER(reg) .cfi_def_cfa_register reg argument
82 #define CFI_RESTORE(reg) .cfi_restore reg argument
83 #define CFI_REL_OFFSET(reg,size) .cfi_rel_offset reg,size argument
91 #define CFI_DEF_CFA(reg,size) argument
92 #define CFI_DEF_CFA_REGISTER(reg) argument
93 #define CFI_RESTORE(reg) argument
94 #define CFI_REL_OFFSET(reg,size) argument
/art/compiler/utils/arm/
Dmanaged_register_arm_test.cc25 ArmManagedRegister reg = ManagedRegister::NoRegister().AsArm(); in TEST() local
31 ArmManagedRegister reg = ArmManagedRegister::FromCoreRegister(R0); in TEST() local
69 ArmManagedRegister reg = ArmManagedRegister::FromSRegister(S0); in TEST() local
126 ArmManagedRegister reg = ArmManagedRegister::FromDRegister(D0); in TEST() local
227 ArmManagedRegister reg = ArmManagedRegister::FromRegisterPair(R0_R1); in TEST() local
459 ArmManagedRegister reg = ArmManagedRegister::FromCoreRegister(R0); in TEST() local
/art/compiler/utils/arm64/
Dmanaged_register_arm64_test.cc26 Arm64ManagedRegister reg = ManagedRegister::NoRegister().AsArm64(); in TEST() local
33 Arm64ManagedRegister reg = Arm64ManagedRegister::FromCoreRegister(X0); in TEST() local
106 Arm64ManagedRegister reg = Arm64ManagedRegister::FromWRegister(W0); in TEST() local
169 Arm64ManagedRegister reg = Arm64ManagedRegister::FromDRegister(D0); in TEST() local
220 Arm64ManagedRegister reg = Arm64ManagedRegister::FromSRegister(S0); in TEST() local
387 Arm64ManagedRegister reg = Arm64ManagedRegister::FromCoreRegister(X0); in TEST() local
/art/compiler/dex/
Dreg_storage.h107 constexpr RegStorage(RegStorageKind rs_kind, int reg) in RegStorage()
183 static constexpr bool IsFloat(uint16_t reg) { in IsFloat()
187 static constexpr bool IsDouble(uint16_t reg) { in IsDouble()
191 static constexpr bool IsSingle(uint16_t reg) { in IsSingle()
195 static constexpr bool Is32Bit(uint16_t reg) { in Is32Bit()
199 static constexpr bool Is64Bit(uint16_t reg) { in Is64Bit()
203 static constexpr bool Is64BitSolo(uint16_t reg) { in Is64BitSolo()
214 void SetReg(int reg) { in SetReg()
221 void SetLowReg(int reg) { in SetLowReg()
250 void SetHighReg(int reg) { in SetHighReg()
Dlocal_value_numbering_test.cc53 #define DEF_CONST(opcode, reg, value) \ argument
55 #define DEF_CONST_WIDE(opcode, reg, value) \ argument
57 #define DEF_CONST_STRING(opcode, reg, index) \ argument
59 #define DEF_IGET(opcode, reg, obj, field_info) \ argument
61 #define DEF_IGET_WIDE(opcode, reg, obj, field_info) \ argument
63 #define DEF_IPUT(opcode, reg, obj, field_info) \ argument
65 #define DEF_IPUT_WIDE(opcode, reg, obj, field_info) \ argument
67 #define DEF_SGET(opcode, reg, field_info) \ argument
69 #define DEF_SGET_WIDE(opcode, reg, field_info) \ argument
71 #define DEF_SPUT(opcode, reg, field_info) \ argument
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Dglobal_value_numbering_test.cc90 #define DEF_CONST(bb, opcode, reg, value) \ argument
92 #define DEF_CONST_WIDE(bb, opcode, reg, value) \ argument
94 #define DEF_CONST_STRING(bb, opcode, reg, index) \ argument
96 #define DEF_IGET(bb, opcode, reg, obj, field_info) \ argument
98 #define DEF_IGET_WIDE(bb, opcode, reg, obj, field_info) \ argument
100 #define DEF_IPUT(bb, opcode, reg, obj, field_info) \ argument
102 #define DEF_IPUT_WIDE(bb, opcode, reg, obj, field_info) \ argument
104 #define DEF_SGET(bb, opcode, reg, field_info) \ argument
106 #define DEF_SGET_WIDE(bb, opcode, reg, field_info) \ argument
108 #define DEF_SPUT(bb, opcode, reg, field_info) \ argument
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/art/compiler/dex/quick/arm64/
Dcodegen_arm64.h269 RegStorage As32BitReg(RegStorage reg) { in As32BitReg()
287 RegStorage Check32BitReg(RegStorage reg) { in Check32BitReg()
305 RegStorage As64BitReg(RegStorage reg) { in As64BitReg()
323 RegStorage Check64BitReg(RegStorage reg) { in Check64BitReg()
/art/runtime/arch/x86_64/
Dcontext_x86_64.h47 uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE { in GetGPRAddress()
52 bool GetGPR(uint32_t reg, uintptr_t* val) OVERRIDE { in GetGPR()
65 bool GetFPR(uint32_t reg, uintptr_t* val) OVERRIDE { in GetFPR()
Dasm_support_x86_64.S80 #define CFI_DEF_CFA(reg,size) .cfi_def_cfa reg,size argument
81 #define CFI_DEF_CFA_REGISTER(reg) .cfi_def_cfa_register reg argument
82 #define CFI_RESTORE(reg) .cfi_restore reg argument
83 #define CFI_REL_OFFSET(reg,size) .cfi_rel_offset reg,size argument
89 #define CFI_DEF_CFA(reg,size) argument
90 #define CFI_DEF_CFA_REGISTER(reg) argument
91 #define CFI_RESTORE(reg) argument
92 #define CFI_REL_OFFSET(reg,size) argument
/art/runtime/arch/arm64/
Dcontext_arm64.h49 uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE { in GetGPRAddress()
54 bool GetGPR(uint32_t reg, uintptr_t* val) OVERRIDE { in GetGPR()
67 bool GetFPR(uint32_t reg, uintptr_t* val) OVERRIDE { in GetFPR()
/art/runtime/arch/arm/
Dcontext_arm.h49 uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE { in GetGPRAddress()
54 bool GetGPR(uint32_t reg, uintptr_t* val) OVERRIDE { in GetGPR()
67 bool GetFPR(uint32_t reg, uintptr_t* val) OVERRIDE { in GetFPR()
/art/runtime/arch/mips/
Dcontext_mips.h48 uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE { in GetGPRAddress()
53 bool GetGPR(uint32_t reg, uintptr_t* val) OVERRIDE { in GetGPR()
66 bool GetFPR(uint32_t reg, uintptr_t* val) OVERRIDE { in GetFPR()
/art/runtime/verifier/
Dregister_line.h302 bool IsSetLockDepth(size_t reg, size_t depth) { in IsSetLockDepth()
311 void SetRegToLockDepth(size_t reg, size_t depth) { in SetRegToLockDepth()
322 void ClearRegToLockDepth(size_t reg, size_t depth) { in ClearRegToLockDepth()
335 void ClearAllRegToLockDepths(size_t reg) { in ClearAllRegToLockDepths()
/art/disassembler/
Ddisassembler_x86.cc66 static void DumpReg0(std::ostream& os, uint8_t rex, size_t reg, in DumpReg0()
83 static void DumpAnyReg(std::ostream& os, uint8_t rex, size_t reg, in DumpAnyReg()
94 static void DumpReg(std::ostream& os, uint8_t rex, uint8_t reg, in DumpReg()
101 static void DumpRmReg(std::ostream& os, uint8_t rex, uint8_t reg, in DumpRmReg()
108 static void DumpAddrReg(std::ostream& os, uint8_t rex, uint8_t reg) { in DumpAddrReg()
116 static void DumpBaseReg(std::ostream& os, uint8_t rex, uint8_t reg) { in DumpBaseReg()
122 static void DumpIndexReg(std::ostream& os, uint8_t rex, uint8_t reg) { in DumpIndexReg()
128 static void DumpOpcodeReg(std::ostream& os, uint8_t rex, uint8_t reg, in DumpOpcodeReg()
/art/compiler/utils/mips/
Dmanaged_register_mips.cc92 std::ostream& operator<<(std::ostream& os, const MipsManagedRegister& reg) { in operator <<()
97 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg) { in operator <<()

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