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Searched defs:target (Results 1 – 25 of 43) sorted by relevance

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/art/compiler/dex/quick/arm/
Dassemble_arm.cc1261 CodeOffset target = lir_target->offset + in AssembleLIR() local
1341 CodeOffset target = target_lir->offset + in AssembleLIR() local
1412 CodeOffset target = target_lir->offset + in AssembleLIR() local
1429 CodeOffset target = target_lir->offset + in AssembleLIR() local
1446 CodeOffset target = target_lir->offset + in AssembleLIR() local
1475 CodeOffset target = lir->operands[1]; in AssembleLIR() local
1492 CodeOffset target = lir->operands[1]; in AssembleLIR() local
1503 LIR* target = lir->target; in AssembleLIR() local
1558 LIR* target = lir->target; in AssembleLIR() local
1568 LIR* target = lir->target; in AssembleLIR() local
Dcall_arm.cc78 LIR* target = NewLIR0(kPseudoTargetLabel); in GenLargeSparseSwitch() local
136 LIR* target = NewLIR0(kPseudoTargetLabel); in GenLargePackedSwitch() local
334 LIR* target = NewLIR0(kPseudoTargetLabel); in MarkGCCard() local
Dint_arm.cc28 LIR* ArmMir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch()
367 LIR* ArmMir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) { in OpCmpImmBranch()
896 LIR* target = NewLIR0(kPseudoTargetLabel); in GenInlinedCas() local
1055 LIR* ArmMir2Lir::OpPcRelLoad(RegStorage reg, LIR* target) { in OpPcRelLoad()
1086 LIR* ArmMir2Lir::OpTestSuspend(LIR* target) { in OpTestSuspend()
1102 LIR* ArmMir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { in OpDecAndBranch()
/art/compiler/dex/quick/mips/
Dassemble_mips.cc582 CodeOffset target = target_lir->offset; in AssembleInstructions() local
596 CodeOffset target = target_lir->offset; in AssembleInstructions() local
610 CodeOffset target = target_lir->offset; in AssembleInstructions() local
623 CodeOffset target = lir->operands[0]; in AssembleInstructions() local
632 CodeOffset target = start_addr + target_lir->offset; in AssembleInstructions() local
636 CodeOffset target = start_addr + target_lir->offset; in AssembleInstructions() local
Dint_mips.cc60 LIR* target = NewLIR0(kPseudoTargetLabel); in GenCmpLong() local
65 LIR* MipsMir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch()
131 LIR* MipsMir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) { in OpCmpImmBranch()
327 LIR* MipsMir2Lir::OpPcRelLoad(RegStorage reg, LIR* target) { in OpPcRelLoad()
363 LIR* MipsMir2Lir::OpTestSuspend(LIR* target) { in OpTestSuspend()
369 LIR* MipsMir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { in OpDecAndBranch()
Dcall_mips.cc209 LIR* target = NewLIR0(kPseudoTargetLabel); in GenLargePackedSwitch() local
283 LIR* target = NewLIR0(kPseudoTargetLabel); in MarkGCCard() local
Dfp_mips.cc171 QuickEntrypointEnum target; in GenCmpFP() local
Dutility_mips.cc110 LIR* MipsMir2Lir::OpUnconditionalBranch(LIR* target) { in OpUnconditionalBranch()
688 LIR* MipsMir2Lir::OpCondBranch(ConditionCode cc, LIR* target) { in OpCondBranch()
/art/compiler/
Delf_patcher.cc208 mirror::ArtMethod* target = GetTargetMethod(patch); in PatchElf() local
258 mirror::ArtMethod* target = GetTargetMethod(patch); in PatchElf() local
263 mirror::Class* target = GetTargetType(patch); in PatchElf() local
268 mirror::String* target = GetTargetString(patch); in PatchElf() local
/art/compiler/sea_ir/code_gen/
Dcode_gen_data.cc43 const ::llvm::Target* target = in GetElf() local
/art/runtime/base/unix_file/
Dfd_file.cc59 void FdFile::moveTo(GuardState target, GuardState warn_threshold, const char* warning) { in moveTo()
70 void FdFile::moveUp(GuardState target, const char* warning) { in moveUp()
/art/compiler/dex/quick/
Dgen_common.cc396 QuickEntrypointEnum target; in GenFilledNewArray() local
471 LIR* target = NewLIR0(kPseudoTargetLabel); in GenFilledNewArray() local
613 QuickEntrypointEnum target = in GenSput() local
695 QuickEntrypointEnum target = in GenSget() local
751 QuickEntrypointEnum target = in GenIGet() local
801 QuickEntrypointEnum target = in GenIPut() local
814 QuickEntrypointEnum target = needs_range_check in GenArrayObjPut() local
1070 LIR* target = NewLIR0(kPseudoTargetLabel); in GenInstanceofFinal() local
1197 LIR* target = NewLIR0(kPseudoTargetLabel); in GenInstanceofCallingHelper() local
1396 QuickEntrypointEnum target; in GenShiftOpLong() local
[all …]
Dmir_to_lir-inl.h45 int op1, int op2, int op3, int op4, LIR* target) { in RawLIR()
/art/compiler/dex/quick/x86/
Dcall_x86.cc123 LIR* target = NewLIR0(kPseudoTargetLabel); in GenLargePackedSwitch() local
200 LIR* target = NewLIR0(kPseudoTargetLabel); in MarkGCCard() local
Dassemble_x86.cc1624 CodeOffset target = target_lir->offset; in AssembleInstructions() local
1651 CodeOffset target = target_lir->offset; in AssembleInstructions() local
1668 CodeOffset target = target_lir->offset; in AssembleInstructions() local
1684 CodeOffset target = target_lir->offset; in AssembleInstructions() local
1710 CodeOffset target = target_lir->offset; in AssembleInstructions() local
1719 CodeOffset target = target_lir->offset; in AssembleInstructions() local
Dutility_x86.cc107 LIR* X86Mir2Lir::OpUnconditionalBranch(LIR* target) { in OpUnconditionalBranch()
113 LIR* X86Mir2Lir::OpCondBranch(ConditionCode cc, LIR* target) { in OpCondBranch()
891 int offset, int check_value, LIR* target, LIR** compare) { in OpCmpMemImmBranch()
Dint_x86.cc96 LIR* X86Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch()
106 int check_value, LIR* target) { in OpCmpImmBranch()
1073 LIR* X86Mir2Lir::OpPcRelLoad(RegStorage reg, LIR* target) { in OpPcRelLoad()
1226 LIR* X86Mir2Lir::OpTestSuspend(LIR* target) { in OpTestSuspend()
1236 LIR* X86Mir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { in OpDecAndBranch()
2682 LIR* target = NewLIR0(kPseudoTargetLabel); in GenInstanceofFinal() local
/art/compiler/optimizing/
Dbuilder.cc147 HBasicBlock* target = FindBlockStartingAt(dex_offset + instruction.GetTargetOffset()); in If_22t() local
163 HBasicBlock* target = FindBlockStartingAt(dex_offset + instruction.GetTargetOffset()); in If_21t() local
248 int32_t target = instruction.GetTargetOffset() + dex_offset; in ComputeBranchTargets() local
581 HBasicBlock* target = FindBlockStartingAt(instruction.GetTargetOffset() + dex_offset); in AnalyzeDexInstruction() local
/art/compiler/dex/quick/arm64/
Dcall_arm64.cc145 LIR* target = NewLIR0(kPseudoTargetLabel); in GenLargePackedSwitch() local
299 LIR* target = NewLIR0(kPseudoTargetLabel); in MarkGCCard() local
Dassemble_arm64.cc861 CodeOffset target = target_lir->offset + in AssembleLIR() local
876 CodeOffset target = target_lir->offset + in AssembleLIR() local
Dint_arm64.cc29 LIR* Arm64Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch()
260 LIR* target) { in OpCmpImmBranch()
289 LIR* target, LIR** compare) { in OpCmpMemImmBranch()
907 LIR* Arm64Mir2Lir::OpPcRelLoad(RegStorage reg, LIR* target) { in OpPcRelLoad()
936 LIR* Arm64Mir2Lir::OpTestSuspend(LIR* target) { in OpTestSuspend()
942 LIR* Arm64Mir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { in OpDecAndBranch()
/art/compiler/llvm/
Dllvm_compilation_unit.cc206 const ::llvm::Target* target = in MaterializeToRawOStream() local
/art/test/046-reflect/src/
DMain.java65 Class target = Target.class; in showStrings() local
83 Class target = otherpackage.Other.class; in checkAccess() local
124 Class target = Target.class; in run() local
/art/runtime/
Dlock_word.h91 static LockWord FromForwardingAddress(size_t target) { in FromForwardingAddress()
/art/disassembler/
Ddisassembler_mips.cc230 uint32_t target = (instr_index << 2); in Dump() local

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