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Searched refs:ConditionCode (Results 1 – 25 of 26) sorted by relevance

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/art/compiler/dex/quick/arm/
Dcodegen_arm.h123 void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,
139 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target);
140 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target);
141 LIR* OpCondBranch(ConditionCode cc, LIR* target);
142 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target);
144 LIR* OpIT(ConditionCode cond, const char* guide);
156 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src);
172 ArmConditionCode ArmConditionEncoding(ConditionCode code);
195 ConditionCode ccode);
Dint_arm.cc28 LIR* ArmMir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch()
43 LIR* ArmMir2Lir::OpIT(ConditionCode ccode, const char* guide) { in OpIT()
156 int64_t val, ConditionCode ccode) { in GenFusedLongCmpImmBranch()
206 void ArmMir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, in GenSelectConst32()
238 ConditionCode ccode = mir->meta.ccode; in GenSelect()
309 ConditionCode ccode = mir->meta.ccode; in GenFusedLongCmpBranch()
367 LIR* ArmMir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) { in OpCmpImmBranch()
1102 LIR* ArmMir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { in OpDecAndBranch()
Dfp_arm.cc233 ConditionCode ccode = mir->meta.ccode; in GenFusedFPCmpBranch()
Dutility_arm.cc213 LIR* ArmMir2Lir::OpCondBranch(ConditionCode cc, LIR* target) { in OpCondBranch()
385 LIR* ArmMir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) { in OpCondRegReg()
Dtarget_arm.cc242 ArmConditionCode ArmMir2Lir::ArmConditionEncoding(ConditionCode ccode) { in ArmConditionEncoding()
/art/compiler/dex/quick/mips/
Dcodegen_mips.h122 void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,
137 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target);
138 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target);
139 LIR* OpCondBranch(ConditionCode cc, LIR* target);
140 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target);
142 LIR* OpIT(ConditionCode cond, const char* guide);
153 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src);
Dint_mips.cc65 LIR* MipsMir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch()
131 LIR* MipsMir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) { in OpCmpImmBranch()
218 void MipsMir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, in GenSelectConst32()
369 LIR* MipsMir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { in OpDecAndBranch()
385 LIR* MipsMir2Lir::OpIT(ConditionCode cond, const char* guide) { in OpIT()
Dutility_mips.cc339 LIR* MipsMir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) { in OpCondRegReg()
688 LIR* MipsMir2Lir::OpCondBranch(ConditionCode cc, LIR* target) { in OpCondBranch()
/art/compiler/dex/quick/arm64/
Dcodegen_arm64.h93 LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg,
188 void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,
205 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) OVERRIDE;
206 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) OVERRIDE;
207 LIR* OpCondBranch(ConditionCode cc, LIR* target) OVERRIDE;
208 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) OVERRIDE;
210 LIR* OpIT(ConditionCode cond, const char* guide) OVERRIDE;
221 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) OVERRIDE;
384 ArmConditionCode ArmConditionEncoding(ConditionCode code);
387 void GenSelect(int32_t left, int32_t right, ConditionCode code, RegStorage rs_dest,
Dint_arm64.cc29 LIR* Arm64Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch()
34 LIR* Arm64Mir2Lir::OpIT(ConditionCode ccode, const char* guide) { in OpIT()
91 void Arm64Mir2Lir::GenSelect(int32_t true_val, int32_t false_val, ConditionCode ccode, in GenSelect()
175 void Arm64Mir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, in GenSelectConst32()
220 ConditionCode ccode = mir->meta.ccode; in GenFusedLongCmpBranch()
259 LIR* Arm64Mir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, in OpCmpImmBranch()
287 LIR* Arm64Mir2Lir::OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, in OpCmpMemImmBranch()
942 LIR* Arm64Mir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { in OpDecAndBranch()
Dfp_arm64.cc219 ConditionCode ccode = mir->meta.ccode; in GenFusedFPCmpBranch()
Dutility_arm64.cc543 LIR* Arm64Mir2Lir::OpCondBranch(ConditionCode cc, LIR* target) { in OpCondBranch()
690 LIR* Arm64Mir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) { in OpCondRegReg()
/art/compiler/dex/quick/x86/
Dcodegen_x86.h240 void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,
264 LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) OVERRIDE;
265 LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value, LIR* target) OVERRIDE;
266 LIR* OpCondBranch(ConditionCode cc, LIR* target) OVERRIDE;
267 LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) OVERRIDE;
269 LIR* OpIT(ConditionCode cond, const char* guide) OVERRIDE;
280 LIR* OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) OVERRIDE;
480 int64_t val, ConditionCode ccode);
780 LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg,
Dint_x86.cc72 X86ConditionCode X86ConditionEncoding(ConditionCode cond) { in X86ConditionEncoding()
96 LIR* X86Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch()
105 LIR* X86Mir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, in OpCmpImmBranch()
209 void X86Mir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, in GenSelectConst32()
277 ConditionCode ccode = mir->meta.ccode; in GenSelect()
335 ConditionCode cc = true_zero_case ? NegateComparison(ccode) : ccode; in GenSelect()
388 ConditionCode ccode = mir->meta.ccode; in GenFusedLongCmpBranch()
448 int64_t val, ConditionCode ccode) { in GenFusedLongCmpImmBranch()
837 ConditionCode condition_code = is_min ? kCondGt : kCondLt; in GenInlinedMinMax()
1236 LIR* X86Mir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) { in OpDecAndBranch()
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Dutility_x86.cc113 LIR* X86Mir2Lir::OpCondBranch(ConditionCode cc, LIR* target) { in OpCondBranch()
356 LIR* X86Mir2Lir::OpCondRegReg(OpKind op, ConditionCode cc, RegStorage r_dest, RegStorage r_src) { in OpCondRegReg()
890 LIR* X86Mir2Lir::OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, in OpCmpMemImmBranch()
Dx86_lir.h748 extern X86ConditionCode X86ConditionEncoding(ConditionCode cond);
Dfp_x86.cc513 ConditionCode ccode = mir->meta.ccode; in GenFusedFPCmpBranch()
/art/compiler/dex/portable/
Dmir_to_gbc.h115 ::llvm::Value* ConvertCompare(ConditionCode cc,
117 void ConvertCompareAndBranch(BasicBlock* bb, MIR* mir, ConditionCode cc,
119 void ConvertCompareZeroAndBranch(BasicBlock* bb, MIR* mir, ConditionCode cc,
Dmir_to_gbc.cc313 ::llvm::Value* MirConverter::ConvertCompare(ConditionCode cc, in ConvertCompare()
330 ConditionCode cc, RegLocation rl_src1, RegLocation rl_src2) { in ConvertCompareAndBranch()
345 MIR* mir, ConditionCode cc, RegLocation rl_src1) { in ConvertCompareZeroAndBranch()
/art/compiler/dex/quick/
Dmir_to_lir.h698 ConditionCode FlipComparisonOrder(ConditionCode before);
699 ConditionCode NegateComparison(ConditionCode before);
828 void GenDivZeroCheck(ConditionCode c_code);
1138 virtual LIR* OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg,
1344 virtual void GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,
1387 virtual LIR* OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) = 0;
1388 virtual LIR* OpCmpImmBranch(ConditionCode cond, RegStorage reg, int check_value,
1390 virtual LIR* OpCondBranch(ConditionCode cc, LIR* target) = 0;
1391 virtual LIR* OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* target) = 0;
1393 virtual LIR* OpIT(ConditionCode cond, const char* guide) = 0;
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Dcodegen_util.cc957 ConditionCode Mir2Lir::FlipComparisonOrder(ConditionCode before) { in FlipComparisonOrder()
958 ConditionCode res; in FlipComparisonOrder()
967 res = static_cast<ConditionCode>(0); in FlipComparisonOrder()
973 ConditionCode Mir2Lir::NegateComparison(ConditionCode before) { in NegateComparison()
974 ConditionCode res; in NegateComparison()
983 res = static_cast<ConditionCode>(0); in NegateComparison()
1210 LIR *Mir2Lir::OpCmpMemImmBranch(ConditionCode cond, RegStorage temp_reg, RegStorage base_reg, in OpCmpMemImmBranch()
Dgen_common.cc56 void Mir2Lir::GenDivZeroCheck(ConditionCode c_code) { in GenDivZeroCheck()
223 ConditionCode cond; in GenCompareAndBranch()
244 cond = static_cast<ConditionCode>(0); in GenCompareAndBranch()
286 ConditionCode cond; in GenCompareZeroAndBranch()
309 cond = static_cast<ConditionCode>(0); in GenCompareZeroAndBranch()
/art/compiler/dex/
Dcompiler_enums.h335 enum ConditionCode { enum
356 std::ostream& operator<<(std::ostream& os, const ConditionCode& kind);
Dmir_optimization.cc208 static constexpr ConditionCode kIfCcZConditionCodes[] = {
219 static constexpr ConditionCode ConditionCodeForIfCcZ(Instruction::Code opcode) { in ConditionCodeForIfCcZ()
Dmir_graph.h360 ConditionCode ccode;

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