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Searched refs:X86Mir2Lir (Results 1 – 8 of 8) sorted by relevance

/art/compiler/dex/quick/x86/
Dtarget_x86.cc179 RegLocation X86Mir2Lir::LocCReturn() { in LocCReturn()
183 RegLocation X86Mir2Lir::LocCReturnRef() { in LocCReturnRef()
187 RegLocation X86Mir2Lir::LocCReturnWide() { in LocCReturnWide()
191 RegLocation X86Mir2Lir::LocCReturnFloat() { in LocCReturnFloat()
195 RegLocation X86Mir2Lir::LocCReturnDouble() { in LocCReturnDouble()
200 RegStorage X86Mir2Lir::TargetReg32(SpecialTargetRegister reg) { in TargetReg32()
234 RegStorage X86Mir2Lir::TargetReg(SpecialTargetRegister reg) { in TargetReg()
242 ResourceMask X86Mir2Lir::GetRegMaskCommon(const RegStorage& reg) const { in GetRegMaskCommon()
249 ResourceMask X86Mir2Lir::GetPCUseDefEncoding() const { in GetPCUseDefEncoding()
253 void X86Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags, in SetupTargetResourceMasks()
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Dutility_x86.cc29 LIR* X86Mir2Lir::OpFpRegCopy(RegStorage r_dest, RegStorage r_src) { in OpFpRegCopy()
56 bool X86Mir2Lir::InexpensiveConstantInt(int32_t value) { in InexpensiveConstantInt()
60 bool X86Mir2Lir::InexpensiveConstantFloat(int32_t value) { in InexpensiveConstantFloat()
64 bool X86Mir2Lir::InexpensiveConstantLong(int64_t value) { in InexpensiveConstantLong()
68 bool X86Mir2Lir::InexpensiveConstantDouble(int64_t value) { in InexpensiveConstantDouble()
81 LIR* X86Mir2Lir::LoadConstantNoClobber(RegStorage r_dest, int value) { in LoadConstantNoClobber()
107 LIR* X86Mir2Lir::OpUnconditionalBranch(LIR* target) { in OpUnconditionalBranch()
113 LIR* X86Mir2Lir::OpCondBranch(ConditionCode cc, LIR* target) { in OpCondBranch()
120 LIR* X86Mir2Lir::OpReg(OpKind op, RegStorage r_dest_src) { in OpReg()
133 LIR* X86Mir2Lir::OpRegImm(OpKind op, RegStorage r_dest_src1, int value) { in OpRegImm()
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Dcall_x86.cc30 void X86Mir2Lir::GenLargeSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) { in GenLargeSparseSwitch()
63 void X86Mir2Lir::GenLargePackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src) { in GenLargePackedSwitch()
137 void X86Mir2Lir::GenFillArrayData(DexOffset table_offset, RegLocation rl_src) { in GenFillArrayData()
175 void X86Mir2Lir::GenMoveException(RegLocation rl_dest) { in GenMoveException()
188 void X86Mir2Lir::MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) { in MarkGCCard()
206 void X86Mir2Lir::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) { in GenEntrySequence()
303 void X86Mir2Lir::GenExitSequence() { in GenExitSequence()
319 void X86Mir2Lir::GenSpecialExitSequence() { in GenSpecialExitSequence()
323 void X86Mir2Lir::GenImplicitNullCheck(RegStorage reg, int opt_flags) { in GenImplicitNullCheck()
Dint_x86.cc34 void X86Mir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1, in GenCmpLong()
96 LIR* X86Mir2Lir::OpCmpBranch(ConditionCode cond, RegStorage src1, RegStorage src2, LIR* target) { in OpCmpBranch()
105 LIR* X86Mir2Lir::OpCmpImmBranch(ConditionCode cond, RegStorage reg, in OpCmpImmBranch()
123 LIR* X86Mir2Lir::OpRegCopyNoInsert(RegStorage r_dest, RegStorage r_src) { in OpRegCopyNoInsert()
141 void X86Mir2Lir::OpRegCopy(RegStorage r_dest, RegStorage r_src) { in OpRegCopy()
148 void X86Mir2Lir::OpRegCopyWide(RegStorage r_dest, RegStorage r_src) { in OpRegCopyWide()
209 void X86Mir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code, in GenSelectConst32()
270 void X86Mir2Lir::GenSelect(BasicBlock* bb, MIR* mir) { in GenSelect()
384 void X86Mir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) { in GenFusedLongCmpBranch()
447 void X86Mir2Lir::GenFusedLongCmpImmBranch(BasicBlock* bb, RegLocation rl_src1, in GenFusedLongCmpImmBranch()
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Dassemble_x86.cc25 const X86EncodingMap X86Mir2Lir::EncodingMap[kX86Last] = {
612 size_t X86Mir2Lir::ComputeSize(const X86EncodingMap* entry, int32_t raw_reg, int32_t raw_index, in ComputeSize()
675 size_t X86Mir2Lir::GetInsnSize(LIR* lir) { in GetInsnSize()
677 const X86EncodingMap* entry = &X86Mir2Lir::EncodingMap[lir->opcode]; in GetInsnSize()
835 ComputeSize(&X86Mir2Lir::EncodingMap[cu_->target64 ? kX86Sub64RI : kX86Sub32RI], in GetInsnSize()
857 void X86Mir2Lir::CheckValidByteRegister(const X86EncodingMap* entry, int32_t raw_reg) { in CheckValidByteRegister()
880 void X86Mir2Lir::EmitPrefix(const X86EncodingMap* entry, in EmitPrefix()
948 void X86Mir2Lir::EmitOpcode(const X86EncodingMap* entry) { in EmitOpcode()
963 void X86Mir2Lir::EmitPrefixAndOpcode(const X86EncodingMap* entry, in EmitPrefixAndOpcode()
969 void X86Mir2Lir::EmitDisp(uint8_t base, int32_t disp) { in EmitDisp()
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Dfp_x86.cc24 void X86Mir2Lir::GenArithOpFloat(Instruction::Code opcode, in GenArithOpFloat()
75 void X86Mir2Lir::GenArithOpDouble(Instruction::Code opcode, in GenArithOpDouble()
125 void X86Mir2Lir::GenLongToFP(RegLocation rl_dest, RegLocation rl_src, bool is_double) { in GenLongToFP()
193 void X86Mir2Lir::GenConversion(Instruction::Code opcode, RegLocation rl_dest, in GenConversion()
342 void X86Mir2Lir::GenRemFP(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2, bool is_do… in GenRemFP()
448 void X86Mir2Lir::GenCmpFP(Instruction::Code code, RegLocation rl_dest, in GenCmpFP()
493 void X86Mir2Lir::GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias, in GenFusedFPCmpBranch()
561 void X86Mir2Lir::GenNegFloat(RegLocation rl_dest, RegLocation rl_src) { in GenNegFloat()
569 void X86Mir2Lir::GenNegDouble(RegLocation rl_dest, RegLocation rl_src) { in GenNegDouble()
586 bool X86Mir2Lir::GenInlinedSqrt(CallInfo* info) { in GenInlinedSqrt()
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Dcodegen_x86.h27 class X86Mir2Lir : public Mir2Lir {
64 X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena);
/art/compiler/dex/quick/
Dgen_invoke.cc1804 reinterpret_cast<X86Mir2Lir*>(this)->CallWithLinkerFixup(target_method, info->type); in GenInvokeNoInline()