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Searched refs:mask (Results 1 – 25 of 29) sorted by relevance

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/art/runtime/arch/arm64/
Dmemcmp16_arm64.S45 #define mask x13 macro
79 mov mask, #~0
80 lsl mask, mask, limit
81 bic data1, data1, mask
82 bic data2, data2, mask
94 mov mask, #0xFFFF
99 and data1, data1, mask
100 and data2, data2, mask
/art/compiler/dex/quick/
Dresource_mask.cc143 const ResourceMask* ResourceMaskCache::GetMask(const ResourceMask& mask) { in GetMask() argument
151 if ((mask.masks_[0] >> 32) == 0u && (mask.masks_[1] & ~kAllowedSpecialBits.masks_[1]) == 0u) { in GetMask()
153 uint32_t low_regs = static_cast<uint32_t>(mask.masks_[0]); in GetMask()
155 if (low_regs_without_lowest == 0u && IsPowerOfTwo(mask.masks_[1])) { in GetMask()
157 size_t index = (mask.masks_[1] != 0u) ? CLZ(mask.masks_[1]) : 0u; in GetMask()
161 } else if (IsPowerOfTwo(low_regs_without_lowest) && mask.masks_[1] == 0u) { in GetMask()
167 } else if (mask.Equals(kEncodeAll)) { in GetMask()
171 DCHECK(res->Equals(mask)) in GetMask()
172 << "(" << std::hex << std::setw(16) << mask.masks_[0] in GetMask()
173 << ", "<< std::hex << std::setw(16) << mask.masks_[1] in GetMask()
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Dmir_to_lir-inl.h143 inline void Mir2Lir::SetupRegMask(ResourceMask* mask, int reg) { in SetupRegMask() argument
146 *mask = mask->Union(reginfo_map_.Get(reg)->DefUseMask()); in SetupRegMask()
152 inline void Mir2Lir::ClearRegMask(ResourceMask* mask, int reg) { in ClearRegMask() argument
155 *mask = mask->ClearBits(reginfo_map_.Get(reg)->DefUseMask()); in ClearRegMask()
Dcodegen_util.cc136 ResourceMask mask; in SetMemRefType() local
142 mask = **mask_ptr; in SetMemRefType()
144 mask.ClearBits(kEncodeMem); in SetMemRefType()
149 mask.SetBit(ResourceMask::kLiteral); in SetMemRefType()
152 mask.SetBit(ResourceMask::kDalvikReg); in SetMemRefType()
155 mask.SetBit(ResourceMask::kHeapRef); in SetMemRefType()
160 mask.SetBit(ResourceMask::kMustNotAlias); in SetMemRefType()
165 *mask_ptr = mask_cache_.GetMask(mask); in SetMemRefType()
Dresource_mask.h157 const ResourceMask* GetMask(const ResourceMask& mask);
Dlocal_optimizations.cc24 #define LOAD_STORE_CHECK_REG_DEP(mask, check) (mask.Intersects(*check->u.m.def_mask)) argument
Dmir_to_lir.h341 RegisterInfo(RegStorage r, const ResourceMask& mask = kEncodeAll);
669 void SetupRegMask(ResourceMask* mask, int reg);
670 void ClearRegMask(ResourceMask* mask, int reg);
1240 virtual void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) = 0;
/art/compiler/dex/quick/mips/
Dtarget_mips.cc287 void MipsMir2Lir::DumpResourceMask(LIR *mips_lir, const ResourceMask& mask, const char *prefix) { in DumpResourceMask() argument
291 if (mask.Equals(kEncodeAll)) { in DumpResourceMask()
298 if (mask.HasBit(i)) { in DumpResourceMask()
304 if (mask.HasBit(ResourceMask::kCCode)) { in DumpResourceMask()
307 if (mask.HasBit(ResourceMask::kFPStatus)) { in DumpResourceMask()
311 if (mips_lir && (mask.HasBit(ResourceMask::kDalvikReg))) { in DumpResourceMask()
316 if (mask.HasBit(ResourceMask::kLiteral)) { in DumpResourceMask()
320 if (mask.HasBit(ResourceMask::kHeapRef)) { in DumpResourceMask()
323 if (mask.HasBit(ResourceMask::kMustNotAlias)) { in DumpResourceMask()
532 uint32_t mask = core_spill_mask_; in SpillCoreRegs() local
[all …]
DREADME.mips31 o Expand the def/use mask (which, unfortunately, is a significant change)
Dcodegen_mips.h72 void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE;
/art/runtime/gc/accounting/
Dspace_bitmap-inl.h38 const uword mask = OffsetToMask(offset); in AtomicTestAndSet() local
45 if ((old_word & mask) != 0) { in AtomicTestAndSet()
49 } while (!atomic_entry->CompareExchangeWeakSequentiallyConsistent(old_word, old_word | mask)); in AtomicTestAndSet()
164 const uword mask = OffsetToMask(offset); in Modify() local
169 *address = old_word | mask; in Modify()
171 *address = old_word & ~mask; in Modify()
174 return (old_word & mask) != 0; in Modify()
/art/compiler/dex/quick/arm64/
Dtarget_arm64.cc308 unsigned mask = (unsigned)(width - 1); in DecodeLogicalImmediate() local
309 DCHECK_NE((imm_s & mask), mask); in DecodeLogicalImmediate()
310 uint64_t bits = BIT_MASK((imm_s & mask) + 1); in DecodeLogicalImmediate()
311 return RepeatBitsAcrossReg(is_wide, RotateRight(bits, imm_r & mask, width), width); in DecodeLogicalImmediate()
520 void Arm64Mir2Lir::DumpResourceMask(LIR* arm_lir, const ResourceMask& mask, const char* prefix) { in DumpResourceMask() argument
524 if (mask.Equals(kEncodeAll)) { in DumpResourceMask()
531 if (mask.HasBit(i)) { in DumpResourceMask()
537 if (mask.HasBit(ResourceMask::kCCode)) { in DumpResourceMask()
540 if (mask.HasBit(ResourceMask::kFPStatus)) { in DumpResourceMask()
545 if (arm_lir && (mask.HasBit(ResourceMask::kDalvikReg))) { in DumpResourceMask()
[all …]
Dutility_arm64.cc257 uint64_t mask = (UINT64_C(1) << (width >> 1)) - 1; in EncodeLogicalImmediate() local
258 if ((value & mask) == ((value >> (width >> 1)) & mask)) { in EncodeLogicalImmediate()
/art/compiler/dex/quick/arm/
Dtarget_arm.cc491 void ArmMir2Lir::DumpResourceMask(LIR* arm_lir, const ResourceMask& mask, const char* prefix) { in DumpResourceMask() argument
495 if (mask.Equals(kEncodeAll)) { in DumpResourceMask()
502 if (mask.HasBit(i)) { in DumpResourceMask()
508 if (mask.HasBit(ResourceMask::kCCode)) { in DumpResourceMask()
511 if (mask.HasBit(ResourceMask::kFPStatus)) { in DumpResourceMask()
516 if (arm_lir && (mask.HasBit(ResourceMask::kDalvikReg))) { in DumpResourceMask()
521 if (mask.HasBit(ResourceMask::kLiteral)) { in DumpResourceMask()
525 if (mask.HasBit(ResourceMask::kHeapRef)) { in DumpResourceMask()
528 if (mask.HasBit(ResourceMask::kMustNotAlias)) { in DumpResourceMask()
Dint_arm.cc44 int mask; in OpIT() local
66 mask = (mask3 << 3) | (mask2 << 2) | (mask1 << 1) | in OpIT()
68 return NewLIR2(kThumb2It, code, mask); in OpIT()
72 int mask; in UpdateIT() local
94 mask = (mask3 << 3) | (mask2 << 2) | (mask1 << 1) | in UpdateIT()
96 it->operands[1] = mask; in UpdateIT()
Dcodegen_arm.h72 void DumpResourceMask(LIR* lir, const ResourceMask& mask, const char* prefix) OVERRIDE;
/art/compiler/dex/quick/x86/
Dtarget_x86.cc397 void X86Mir2Lir::DumpResourceMask(LIR *x86LIR, const ResourceMask& mask, const char *prefix) { in DumpResourceMask() argument
401 if (mask.Equals(kEncodeAll)) { in DumpResourceMask()
408 if (mask.HasBit(i)) { in DumpResourceMask()
414 if (mask.HasBit(ResourceMask::kCCode)) { in DumpResourceMask()
418 if (x86LIR && (mask.HasBit(ResourceMask::kDalvikReg))) { in DumpResourceMask()
423 if (mask.HasBit(ResourceMask::kLiteral)) { in DumpResourceMask()
427 if (mask.HasBit(ResourceMask::kHeapRef)) { in DumpResourceMask()
430 if (mask.HasBit(ResourceMask::kMustNotAlias)) { in DumpResourceMask()
696 uint32_t mask = core_spill_mask_ & ~(1 << rs_rRET.GetRegNum()); in SpillCoreRegs() local
699 for (int reg = 0; mask; mask >>= 1, reg++) { in SpillCoreRegs()
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/art/runtime/
Dinstruction_set.h189 explicit InstructionSetFeatures(uint32_t mask) : mask_(mask) {} in InstructionSetFeatures() argument
Dstack_map.h176 void SetRegisterMask(uint32_t mask) { in SetRegisterMask() argument
177 region_.Store<uint32_t>(kRegisterMaskOffset, mask); in SetRegisterMask()
Dstack.cc283 uint64_t mask = 0xffffffff; in SetVReg() local
285 mask = mask << 32; in SetVReg()
289 new_value = static_cast<uintptr_t>((old_reg_val_as_wide & mask) | new_vreg_portion); in SetVReg()
Dmem_map.cc111 constexpr uintptr_t mask = mask_ones & ~(kPageSize - 1); in CreateStartPos() local
114 return (input & mask) + LOW_MEM_START; in CreateStartPos()
/art/disassembler/
Ddisassembler_mips.cc29 uint32_t mask; member
35 return (instruction & mask) == value; in Matches()
Ddisassembler_arm.cc1873 uint32_t mask = opB; in DumpThumb16() local
1878 size_t count = 3 - CTZ(mask); in DumpThumb16()
1882 bool positive_mask = ((mask & (1 << (3 - i))) != 0); in DumpThumb16()
/art/runtime/gc/allocator/
Drosalloc.cc867 const uint32_t mask = 1U << ffz; in AllocSlot() local
870 DCHECK_EQ(*alloc_bitmap_ptr & mask, 0U); in AllocSlot()
871 *alloc_bitmap_ptr |= mask; in AllocSlot()
872 DCHECK_NE(*alloc_bitmap_ptr & mask, 0U); in AllocSlot()
908 const uint32_t mask = 1U << vec_off; in FreeSlot() local
909 DCHECK_NE(*vec & mask, 0U); in FreeSlot()
910 *vec &= ~mask; in FreeSlot()
911 DCHECK_EQ(*vec & mask, 0U); in FreeSlot()
1020 const uint32_t mask = 1U << vec_off; in MarkFreeBitMapShared() local
1021 DCHECK_EQ(*vec & mask, 0U); in MarkFreeBitMapShared()
[all …]
/art/runtime/mirror/
Dart_method.h128 uint32_t mask = kAccFastNative | kAccNative; in IsFastNative() local
129 return (GetAccessFlags() & mask) == mask; in IsFastNative()

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